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The enablement code for the PMU is scattered and difficult to track down. Factor out the feature into its own lib/extensions folder and consolidate the implementation. Treat it is as an architecturally mandatory feature as it is currently. Additionally, do some cleanup on AArch64. Setting overflow bits in PMCR_EL0 is irrelevant for firmware so don't do it. Then delay the PMU initialisation until the context management stage which simplifies the early environment assembly. One side effect is that the PMU might count before this happens so reset all counters to 0 to prevent any leakage. Finally, add an enable to manage_extensions_realm() as realm world uses the pmu. This introduces the HPMN fixup to realm world. Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: Ie13a8625820ecc5fbfa467dc6ca18025bf6a9cd3pull/1999/head
Boyan Karatotev
2 years ago
committed by
Jayanth Dodderi Chidanand
Jayanth Dodderi Chidanand
16 changed files with 276 additions and 102 deletions
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/*
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* Copyright (c) 2023, Arm Limited. All rights reserved. |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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#ifndef PMUV3_H |
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#define PMUV3_H |
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#include <context.h> |
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void pmuv3_disable_el3(void); |
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#ifdef __aarch64__ |
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void pmuv3_enable(cpu_context_t *ctx); |
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void pmuv3_init_el2_unused(void); |
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#endif /* __aarch64__ */ |
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#endif /* PMUV3_H */ |
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/*
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* Copyright (c) 2023, Arm Limited. All rights reserved. |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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#include <arch.h> |
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#include <arch_features.h> |
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#include <arch_helpers.h> |
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#include <lib/extensions/pmuv3.h> |
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/*
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* Applies to all PMU versions. Name is PMUv3 for compatibility with aarch64 and |
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* to not clash with platforms which reuse the PMU name |
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*/ |
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void pmuv3_disable_el3(void) |
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{ |
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u_register_t sdcr = read_sdcr(); |
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/* ---------------------------------------------------------------------
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* Initialise SDCR, setting all the fields rather than relying on hw. |
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* |
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* SDCR.SCCD: Set to one so that cycle counting by PMCCNTR is prohibited |
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* in Secure state. This bit is RES0 in versions of the architecture |
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* earlier than ARMv8.5 |
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* |
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* SDCR.SPME: Set to zero so that event counting is prohibited in Secure |
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* state (and explicitly EL3 with later revisions). If ARMv8.2 Debug is |
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* not implemented this bit does not have any effect on the counters |
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* unless there is support for the implementation defined |
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* authentication interface ExternalSecureNoninvasiveDebugEnabled(). |
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* --------------------------------------------------------------------- |
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*/ |
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sdcr = (sdcr | SDCR_SCCD_BIT) & ~SDCR_SPME_BIT; |
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write_sdcr(sdcr); |
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/* ---------------------------------------------------------------------
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* Initialise PMCR, setting all fields rather than relying |
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* on hw. Some fields are architecturally UNKNOWN on reset. |
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* |
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* PMCR.DP: Set to one to prohibit cycle counting whilst in Secure mode. |
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* |
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* PMCR.X: Set to zero to disable export of events. |
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* |
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* PMCR.C: Set to one to reset PMCCNTR. |
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* |
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* PMCR.P: Set to one to reset each event counter PMEVCNTR<n> to zero. |
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* |
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* PMCR.E: Set to zero to disable cycle and event counters. |
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* --------------------------------------------------------------------- |
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*/ |
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write_pmcr(read_pmcr() | PMCR_DP_BIT | PMCR_C_BIT | PMCR_P_BIT | |
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~(PMCR_X_BIT | PMCR_E_BIT)); |
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} |
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/*
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* Copyright (c) 2023, Arm Limited. All rights reserved. |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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#include <arch.h> |
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#include <arch_features.h> |
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#include <arch_helpers.h> |
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#include <lib/extensions/pmuv3.h> |
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static u_register_t init_mdcr_el2_hpmn(u_register_t mdcr_el2) |
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{ |
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/*
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* Initialize MDCR_EL2.HPMN to its hardware reset value so we don't |
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* throw anyone off who expects this to be sensible. |
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*/ |
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mdcr_el2 &= ~MDCR_EL2_HPMN_MASK; |
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mdcr_el2 |= ((read_pmcr_el0() >> PMCR_EL0_N_SHIFT) & PMCR_EL0_N_MASK); |
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return mdcr_el2; |
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} |
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void pmuv3_enable(cpu_context_t *ctx) |
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{ |
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#if CTX_INCLUDE_EL2_REGS |
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u_register_t mdcr_el2; |
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mdcr_el2 = read_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_MDCR_EL2); |
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mdcr_el2 = init_mdcr_el2_hpmn(mdcr_el2); |
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write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_MDCR_EL2, mdcr_el2); |
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#endif /* CTX_INCLUDE_EL2_REGS */ |
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} |
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void pmuv3_disable_el3(void) |
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{ |
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u_register_t mdcr_el3 = read_mdcr_el3(); |
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/* ---------------------------------------------------------------------
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* Initialise MDCR_EL3, setting all fields rather than relying on hw. |
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* Some fields are architecturally UNKNOWN on reset. |
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* |
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* MDCR_EL3.MPMX: Set to zero to not affect event counters (when |
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* SPME = 0). |
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* |
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* MDCR_EL3.MCCD: Set to one so that cycle counting by PMCCNTR_EL0 is |
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* prohibited in EL3. This bit is RES0 in versions of the |
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* architecture with FEAT_PMUv3p7 not implemented. |
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* |
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* MDCR_EL3.SCCD: Set to one so that cycle counting by PMCCNTR_EL0 is |
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* prohibited in Secure state. This bit is RES0 in versions of the |
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* architecture with FEAT_PMUv3p5 not implemented. |
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* |
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* MDCR_EL3.SPME: Set to zero so that event counting is prohibited in |
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* Secure state (and explicitly EL3 with later revisions). If ARMv8.2 |
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* Debug is not implemented this bit does not have any effect on the |
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* counters unless there is support for the implementation defined |
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* authentication interface ExternalSecureNoninvasiveDebugEnabled(). |
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* |
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* The SPME/MPMX combination is a little tricky. Below is a small |
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* summary if another combination is ever needed: |
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* SPME | MPMX | secure world | EL3 |
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* ------------------------------------- |
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* 0 | 0 | disabled | disabled |
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* 1 | 0 | enabled | enabled |
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* 0 | 1 | enabled | disabled |
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* 1 | 1 | enabled | disabled only for counters 0 to |
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* MDCR_EL2.HPMN - 1. Enabled for the rest |
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*/ |
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mdcr_el3 = (mdcr_el3 | MDCR_SCCD_BIT | MDCR_MCCD_BIT) & |
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~(MDCR_MPMX_BIT | MDCR_SPME_BIT); |
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write_mdcr_el3(mdcr_el3); |
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/* ---------------------------------------------------------------------
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* Initialise PMCR_EL0 setting all fields rather than relying |
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* on hw. Some fields are architecturally UNKNOWN on reset. |
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* |
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* PMCR_EL0.DP: Set to one so that the cycle counter, |
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* PMCCNTR_EL0 does not count when event counting is prohibited. |
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* Necessary on PMUv3 <= p7 where MDCR_EL3.{SCCD,MCCD} are not |
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* available |
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* |
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* PMCR_EL0.X: Set to zero to disable export of events. |
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* |
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* PMCR_EL0.C: Set to one to reset PMCCNTR_EL0 to zero. |
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* |
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* PMCR_EL0.P: Set to one to reset each event counter PMEVCNTR<n>_EL0 to |
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* zero. |
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* |
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* PMCR_EL0.E: Set to zero to disable cycle and event counters. |
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* --------------------------------------------------------------------- |
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*/ |
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write_pmcr_el0((read_pmcr_el0() | PMCR_EL0_DP_BIT | PMCR_EL0_C_BIT | |
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PMCR_EL0_P_BIT) & ~(PMCR_EL0_X_BIT | PMCR_EL0_E_BIT)); |
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} |
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void pmuv3_init_el2_unused(void) |
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{ |
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u_register_t mdcr_el2 = read_mdcr_el2(); |
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/*
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* Initialise MDCR_EL2, setting all fields rather than |
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* relying on hw. Some fields are architecturally |
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* UNKNOWN on reset. |
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* |
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* MDCR_EL2.HLP: Set to one so that event counter overflow, that is |
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* recorded in PMOVSCLR_EL0[0-30], occurs on the increment that changes |
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* PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU is implemented. |
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* This bit is RES0 in versions of the architecture earlier than |
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* ARMv8.5, setting it to 1 doesn't have any effect on them. |
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* |
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* MDCR_EL2.HCCD: Set to one to prohibit cycle counting at EL2. This bit |
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* is RES0 in versions of the architecture with FEAT_PMUv3p5 not |
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* implemented. |
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* |
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* MDCR_EL2.HPMD: Set to one so that event counting is |
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* prohibited at EL2 for counter n < MDCR_EL2.HPMN. This bit is RES0 |
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* in versions of the architecture with FEAT_PMUv3p1 not implemented. |
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* |
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* MDCR_EL2.HPME: Set to zero to disable event counters for counters |
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* n >= MDCR_EL2.HPMN. |
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* |
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* MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and |
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* EL1 accesses to all Performance Monitors registers |
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* are not trapped to EL2. |
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* |
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* MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0 |
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* and EL1 accesses to the PMCR_EL0 or PMCR are not |
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* trapped to EL2. |
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*/ |
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mdcr_el2 = (mdcr_el2 | MDCR_EL2_HLP_BIT | MDCR_EL2_HPMD_BIT | |
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MDCR_EL2_HCCD_BIT) & |
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~(MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT | MDCR_EL2_TPMCR_BIT); |
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mdcr_el2 = init_mdcr_el2_hpmn(mdcr_el2); |
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write_mdcr_el2(mdcr_el2); |
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} |
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