From 81646055138ed431ca155382ccf7c286f4d52e7f Mon Sep 17 00:00:00 2001 From: Grzegorz Jaszczyk Date: Fri, 18 Aug 2017 16:42:12 +0200 Subject: [PATCH 1/2] plat: marvell: armada: add support for loading MG CM3 images In order to access MG SRAM, the amb bridge needs to be configured which is done in bl2 platform init. For MG CM3, the image is only loaded to its SRAM and the CM3 itself is left in reset. It is because the next stage bootloader (e.g. u-boot) will trigger action which will take it out of reset when needed. This can happen e.g. when appropriate device-tree setup (which has enabled 802.3 auto-neg) will be chosen. In other cases the MG CM3 should not be running. Change-Id: I816ea14e3a7174eace068ec44e3cc09998d0337e Signed-off-by: Grzegorz Jaszczyk --- drivers/marvell/mochi/cp110_setup.c | 6 ++-- include/drivers/marvell/mochi/cp110_setup.h | 1 + plat/marvell/a8k/common/mss/mss_a8k.mk | 3 +- plat/marvell/a8k/common/mss/mss_bl2_setup.c | 6 ++++ plat/marvell/common/mss/mss_scp_bootloader.c | 37 +++++++++++++++++--- 5 files changed, 44 insertions(+), 9 deletions(-) diff --git a/drivers/marvell/mochi/cp110_setup.c b/drivers/marvell/mochi/cp110_setup.c index b4b4e0c82..7186f9857 100644 --- a/drivers/marvell/mochi/cp110_setup.c +++ b/drivers/marvell/mochi/cp110_setup.c @@ -303,7 +303,7 @@ static void cp110_axi_attr_init(uintptr_t base) DOMAIN_SYSTEM_SHAREABLE); } -static void amb_bridge_init(uintptr_t base) +void cp110_amb_init(uintptr_t base) { uint32_t reg; @@ -399,7 +399,7 @@ void cp110_init(uintptr_t cp110_base, uint32_t stream_id) cp110_stream_id_init(cp110_base, stream_id); /* Open AMB bridge for comphy for CP0 & CP1*/ - amb_bridge_init(cp110_base); + cp110_amb_init(cp110_base); /* Reset RTC if needed */ cp110_rtc_init(cp110_base); @@ -411,7 +411,7 @@ void cp110_ble_init(uintptr_t cp110_base) #if PCI_EP_SUPPORT INFO("%s: Initialize CPx - base = %lx\n", __func__, cp110_base); - amb_bridge_init(cp110_base); + cp110_amb_init(cp110_base); /* Configure PCIe clock */ cp110_pcie_clk_cfg(cp110_base); diff --git a/include/drivers/marvell/mochi/cp110_setup.h b/include/drivers/marvell/mochi/cp110_setup.h index 3686257d3..f8cd26b12 100644 --- a/include/drivers/marvell/mochi/cp110_setup.h +++ b/include/drivers/marvell/mochi/cp110_setup.h @@ -51,5 +51,6 @@ static inline uint32_t cp110_rev_id_get(uintptr_t base) void cp110_init(uintptr_t cp110_base, uint32_t stream_id); void cp110_ble_init(uintptr_t cp110_base); +void cp110_amb_init(uintptr_t base); #endif /* CP110_SETUP_H */ diff --git a/plat/marvell/a8k/common/mss/mss_a8k.mk b/plat/marvell/a8k/common/mss/mss_a8k.mk index 58f23d8dd..efd03c5a2 100644 --- a/plat/marvell/a8k/common/mss/mss_a8k.mk +++ b/plat/marvell/a8k/common/mss/mss_a8k.mk @@ -8,7 +8,8 @@ PLAT_MARVELL := plat/marvell A8K_MSS_SOURCE := $(PLAT_MARVELL)/a8k/common/mss -BL2_SOURCES += $(A8K_MSS_SOURCE)/mss_bl2_setup.c +BL2_SOURCES += $(A8K_MSS_SOURCE)/mss_bl2_setup.c \ + $(MARVELL_MOCHI_DRV) BL31_SOURCES += $(A8K_MSS_SOURCE)/mss_pm_ipc.c diff --git a/plat/marvell/a8k/common/mss/mss_bl2_setup.c b/plat/marvell/a8k/common/mss/mss_bl2_setup.c index 728ee54a0..09b8446fa 100644 --- a/plat/marvell/a8k/common/mss/mss_bl2_setup.c +++ b/plat/marvell/a8k/common/mss/mss_bl2_setup.c @@ -74,6 +74,12 @@ static int bl2_plat_mmap_init(void) /* Set the default target id to PIDI */ mmio_write_32(MVEBU_IO_WIN_BASE(MVEBU_AP0) + IOW_GCR_OFFSET, PIDI_TID); + /* Open AMB bridge required for MG access */ + cp110_amb_init(MVEBU_CP_REGS_BASE(0)); + + if (CP_COUNT == 2) + cp110_amb_init(MVEBU_CP_REGS_BASE(1)); + return 0; } diff --git a/plat/marvell/common/mss/mss_scp_bootloader.c b/plat/marvell/common/mss/mss_scp_bootloader.c index 7e442c615..2f1c46f47 100644 --- a/plat/marvell/common/mss/mss_scp_bootloader.c +++ b/plat/marvell/common/mss/mss_scp_bootloader.c @@ -42,6 +42,8 @@ #define MSS_HANDSHAKE_TIMEOUT 50 +#define MG_CM3_SRAM_BASE(CP) (MVEBU_CP_REGS_BASE(CP) + 0x100000) + static int mss_check_image_ready(volatile struct mss_pm_ctrl_block *mss_pm_crtl) { int timeout = MSS_HANDSHAKE_TIMEOUT; @@ -59,6 +61,28 @@ static int mss_check_image_ready(volatile struct mss_pm_ctrl_block *mss_pm_crtl) return 0; } +static int mg_image_load(uintptr_t src_addr, uint32_t size, uintptr_t mg_regs) +{ + if (size > MG_SRAM_SIZE) { + ERROR("image is too big to fit into MG CM3 memory\n"); + return 1; + } + + NOTICE("Loading MG image from address 0x%lx Size 0x%x to MG at 0x%lx\n", + src_addr, size, mg_regs); + + /* Copy image to MG CM3 SRAM */ + memcpy((void *)mg_regs, (void *)src_addr, size); + + /* + * Don't release MG CM3 from reset - it will be done by next step + * bootloader (e.g. U-Boot), when appriopriate device-tree setup (which + * has enabeld 802.3. auto-neg) will be choosen. + */ + + return 0; +} + static int mss_image_load(uint32_t src_addr, uint32_t size, uintptr_t mss_regs) { uint32_t i, loop_num, timeout; @@ -225,12 +249,15 @@ static int load_img_to_cm3(enum cm3_t cm3_type, } break; case MG_CP0: - /* TODO: */ - NOTICE("Load image to CP0 MG not supported\n"); - break; case MG_CP1: - /* TODO: */ - NOTICE("Load image to CP1 MG not supported\n"); + cp_index = cm3_type - MG_CP0; + NOTICE("Load image to CP%d MG\n", cp_index); + ret = mg_image_load(single_img, image_size, + MG_CM3_SRAM_BASE(cp_index)); + if (ret != 0) { + ERROR("SCP Image load failed\n"); + return -1; + } break; default: ERROR("SCP_BL2 wrong img format (cm3_type=%d)\n", cm3_type); From 621146d851d474359f7d577b83a5424d1682f622 Mon Sep 17 00:00:00 2001 From: Grzegorz Jaszczyk Date: Thu, 4 Apr 2019 14:38:55 +0200 Subject: [PATCH 2/2] plat: marvell: armada: scp_bl2: allow loading up to 8 images Extend possible images to 8, additionaly add another type which will be used with platform containing up to 3 CPs. Change-Id: Ib68092d11af9801e344d02de839f53127e056e46 Signed-off-by: Grzegorz Jaszczyk --- plat/marvell/common/mss/mss_scp_bl2_format.h | 3 ++- plat/marvell/common/mss/mss_scp_bootloader.c | 8 +++++++- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/plat/marvell/common/mss/mss_scp_bl2_format.h b/plat/marvell/common/mss/mss_scp_bl2_format.h index 7cf8d3201..7150f0a06 100644 --- a/plat/marvell/common/mss/mss_scp_bl2_format.h +++ b/plat/marvell/common/mss/mss_scp_bl2_format.h @@ -8,7 +8,7 @@ #ifndef MSS_SCP_BL2_FORMAT_H #define MSS_SCP_BL2_FORMAT_H -#define MAX_NR_OF_FILES 5 +#define MAX_NR_OF_FILES 8 #define FILE_MAGIC 0xddd01ff #define HEADER_VERSION 0x1 @@ -31,6 +31,7 @@ enum cm3_t { MSS_CP3, MG_CP0, MG_CP1, + MG_CP2, }; typedef struct img_header { diff --git a/plat/marvell/common/mss/mss_scp_bootloader.c b/plat/marvell/common/mss/mss_scp_bootloader.c index 2f1c46f47..4473d81e1 100644 --- a/plat/marvell/common/mss/mss_scp_bootloader.c +++ b/plat/marvell/common/mss/mss_scp_bootloader.c @@ -250,7 +250,13 @@ static int load_img_to_cm3(enum cm3_t cm3_type, break; case MG_CP0: case MG_CP1: + case MG_CP2: cp_index = cm3_type - MG_CP0; + if (bl2_plat_get_cp_count(0) <= cp_index) { + NOTICE("Skipping MG CP%d related image\n", + cp_index); + break; + } NOTICE("Load image to CP%d MG\n", cp_index); ret = mg_image_load(single_img, image_size, MG_CM3_SRAM_BASE(cp_index)); @@ -288,7 +294,7 @@ static int split_and_load_bl2_image(void *image) } if (file_hdr->nr_of_imgs > MAX_NR_OF_FILES) { - ERROR("SCP_BL2 concatenated image contains to many images\n"); + ERROR("SCP_BL2 concatenated image contains too many images\n"); return -1; }