From 2f1b4c55502262dba0ccd147f87cdb38cf4131f2 Mon Sep 17 00:00:00 2001 From: Akshay Belsare Date: Fri, 13 Jan 2023 14:40:37 +0530 Subject: [PATCH] feat(versal-net): add support for uart1 console Versal NET platform supports two UART(UART0, UART1) Add support for UART1 to be used as console for Versal NET platform. Change-Id: I3bc2034f54052e37cc480f98d48335fa5b2138bf Signed-off-by: Akshay Belsare --- plat/xilinx/versal_net/include/versal_net_def.h | 8 ++++++++ plat/xilinx/versal_net/platform.mk | 5 +++++ 2 files changed, 13 insertions(+) diff --git a/plat/xilinx/versal_net/include/versal_net_def.h b/plat/xilinx/versal_net/include/versal_net_def.h index 929186aae..14e63d575 100644 --- a/plat/xilinx/versal_net/include/versal_net_def.h +++ b/plat/xilinx/versal_net/include/versal_net_def.h @@ -138,9 +138,17 @@ * UART related constants ******************************************************************************/ #define VERSAL_NET_UART0_BASE U(0xF1920000) +#define VERSAL_NET_UART1_BASE U(0xF1930000) + #define VERSAL_NET_UART_BAUDRATE 115200 +#if VERSAL_NET_CONSOLE_IS(pl011) || VERSAL_NET_CONSOLE_IS(pl011_0) #define VERSAL_NET_UART_BASE VERSAL_NET_UART0_BASE +#elif VERSAL_NET_CONSOLE_IS(pl011_1) +#define VERSAL_NET_UART_BASE VERSAL_NET_UART1_BASE +#else +# error "invalid VERSAL_NET_CONSOLE" +#endif #define PLAT_VERSAL_NET_CRASH_UART_BASE VERSAL_NET_UART_BASE #define PLAT_VERSAL_NET_CRASH_UART_CLK_IN_HZ VERSAL_NET_UART_CLOCK diff --git a/plat/xilinx/versal_net/platform.mk b/plat/xilinx/versal_net/platform.mk index b3d56bcc4..622ae98c2 100644 --- a/plat/xilinx/versal_net/platform.mk +++ b/plat/xilinx/versal_net/platform.mk @@ -53,6 +53,11 @@ USE_COHERENT_MEM := 0 HW_ASSISTED_COHERENCY := 1 VERSAL_NET_CONSOLE ?= pl011 +ifeq (${VERSAL_NET_CONSOLE}, $(filter ${VERSAL_NET_CONSOLE},pl011 pl011_0 pl011_1)) +else + $(error Please define VERSAL_NET_CONSOLE) +endif + $(eval $(call add_define_val,VERSAL_NET_CONSOLE,VERSAL_NET_CONSOLE_ID_${VERSAL_NET_CONSOLE})) PLAT_INCLUDES := -Iinclude/plat/arm/common/ \