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@ -623,6 +623,62 @@ General Threats for All Firmware Images |
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| | UART interface(s). | |
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| ID | 16 | |
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| Threat | | **An attacker could analyse the timing behaviour | |
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| | of implemented methods in the system to infer | |
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| | sensitive information.** | |
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| | | A timing side-channel attack is a type of attack | |
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| | that exploits variations in the time it takes a | |
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| | system to perform different operations. This | |
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| | form of attack focuses on analyzing the time- | |
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| | related information leakage that occurs during | |
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| | the execution of cryptographic algorithms or | |
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| | other security-sensitive processes. By observing | |
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| | these timing differences, an attacker can gain | |
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| | insights into the internal workings of a system | |
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| | and potentially extract sensitive information. | |
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| | Sensitive information that, when revealed even | |
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| | partially, could heighten the susceptibility to | |
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| | traditional attacks like brute-force attacks. | |
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| Diagram Elements | DF2 | |
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| Affected TF-A | BL1, BL2, BL31 | |
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| Components | | |
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| Assets | Sensitive Data | |
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| Threat Agent | AppDebug | |
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| Threat Type | Information Disclosure | |
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+------------------------+------------------+----------------+-----------------+ |
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| Application | Server | IoT | Mobile | |
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+------------------------+------------------+----------------+-----------------+ |
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| Impact | Critical (5) | Critical (5) | Critical (5) | |
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+------------------------+------------------+----------------+-----------------+ |
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| Likelihood | Critical (5) | Critical (5) | Critical (5) | |
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+------------------------+------------------+----------------+-----------------+ |
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| Total Risk Rating | Critical (25) | Critical (25) | Critical (25) | |
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+------------------------+------------------+----------------+-----------------+ |
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| Mitigations | | Ensure that the execution time of critical | |
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| | operations is constant and independent of | |
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| | secret data. This prevents attackers from | |
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| | exploiting timing differences to infer | |
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| | information about sensitive data. | |
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| | | |
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| | | Introduce random delays/timing jitter or dummy | |
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| | operations to make the timing behavior of program| |
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| | execution less predictable. This can disrupt the | |
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| | correlation between the execution time and | |
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| | sensitive data. | |
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+------------------------+-----------------------------------------------------+ |
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| Mitigations | | Not implemented | |
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| implemented? | | |
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.. _Boot Firmware Threats: |
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