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intel: Enable EMAC PHY in Intel FPGA platform 

This initializes the EMAC PHY in both Stratix 10 and Agilex,
without this, EMAC PHY wouldn't work correctly.

Change-Id: I7e6b9e88fd9ef472884fcf648e6001fcb7549ae6
Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
pull/1938/head
Tien Hock, Loh 5 years ago
committed by Abdul Halim, Muhammad Hadi Asyrafi
parent
2f39c55c08
commit
d603fd3033
8 changed files with 91 additions and 10 deletions
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  1. 6
      plat/intel/soc/agilex/bl2_plat_setup.c
  2. 5
      plat/intel/soc/agilex/platform.mk
  3. 12
      plat/intel/soc/common/include/platform_def.h
  4. 24
      plat/intel/soc/common/include/socfpga_emac.h
  5. 5
      plat/intel/soc/common/include/socfpga_system_manager.h
  6. 38
      plat/intel/soc/common/soc/socfpga_emac.c
  7. 6
      plat/intel/soc/stratix10/bl2_plat_setup.c
  8. 5
      plat/intel/soc/stratix10/platform.mk

6
plat/intel/soc/agilex/bl2_plat_setup.c
View File

@ -1,6 +1,6 @@
/*
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2019, Intel Corporation. All rights reserved.
* Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -20,6 +20,7 @@
#include "agilex_pinmux.h"
#include "ccu/ncore_ccu.h"
#include "qspi/cadence_qspi.h"
#include "socfpga_emac.h"
#include "socfpga_handoff.h"
#include "socfpga_mailbox.h"
#include "socfpga_private.h"
@ -72,6 +73,7 @@ void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1,
socfpga_delay_timer_init();
init_ncore_ccu();
socfpga_emac_init();
init_hard_memory_controller();
mailbox_init();

5
plat/intel/soc/agilex/platform.mk
View File

@ -1,6 +1,6 @@
#
# Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
# Copyright (c) 2019, Intel Corporation. All rights reserved.
# Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
# Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@ -42,6 +42,7 @@ BL2_SOURCES += \
plat/intel/soc/common/socfpga_delay_timer.c \
plat/intel/soc/common/socfpga_image_load.c \
plat/intel/soc/common/socfpga_storage.c \
plat/intel/soc/common/soc/socfpga_emac.c \
plat/intel/soc/common/soc/socfpga_handoff.c \
plat/intel/soc/common/soc/socfpga_mailbox.c \
plat/intel/soc/common/soc/socfpga_reset_manager.c \

12
plat/intel/soc/common/include/platform_def.h
View File

@ -1,6 +1,6 @@
/*
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2019, Intel Corporation. All rights reserved.
* Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -168,6 +168,14 @@
#define PLAT_BAUDRATE (115200)
#define PLAT_UART_CLOCK (100000000)
/*******************************************************************************
* PHY related constants
******************************************************************************/
#define EMAC0_PHY_MODE PHY_INTERFACE_MODE_RGMII
#define EMAC1_PHY_MODE PHY_INTERFACE_MODE_RGMII
#define EMAC2_PHY_MODE PHY_INTERFACE_MODE_RGMII
/*******************************************************************************
* System counter frequency related constants
******************************************************************************/

24
plat/intel/soc/common/include/socfpga_emac.h
View File

@ -0,0 +1,24 @@
/*
* Copyright (c) 2020, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef SOCFPGA_EMAC_H
#define SOCFPGA_EMAC_H
/* EMAC PHY Mode */
#define PHY_INTERFACE_MODE_GMII_MII 0
#define PHY_INTERFACE_MODE_RGMII 1
#define PHY_INTERFACE_MODE_RMII 2
#define PHY_INTERFACE_MODE_RESET 3
/* Mask Definitions */
#define PHY_INTF_SEL_MSK 0x3
#define FPGAINTF_EN_3_EMAC_MSK(x) (1 << (x * 8))
void socfpga_emac_init(void);
#endif /* SOCFPGA_EMAC_H */

5
plat/intel/soc/common/include/socfpga_system_manager.h
View File

@ -13,6 +13,11 @@
#define SOCFPGA_SYSMGR_SDMMC 0x28
#define SOCFPGA_SYSMGR_EMAC_0 0x44
#define SOCFPGA_SYSMGR_EMAC_1 0x48
#define SOCFPGA_SYSMGR_EMAC_2 0x4c
#define SOCFPGA_SYSMGR_FPGAINTF_EN_3 0x70
#define SOCFPGA_SYSMGR_NOC_TIMEOUT 0xc0
#define SOCFPGA_SYSMGR_NOC_IDLEREQ_SET 0xc4
#define SOCFPGA_SYSMGR_NOC_IDLEREQ_CLR 0xc8

38
plat/intel/soc/common/soc/socfpga_emac.c
View File

@ -0,0 +1,38 @@
/*
* Copyright (c) 2020, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <lib/mmio.h>
#include <platform_def.h>
#include "socfpga_emac.h"
#include "socfpga_reset_manager.h"
#include "socfpga_system_manager.h"
void socfpga_emac_init(void)
{
mmio_setbits_32(SOCFPGA_RSTMGR(PER0MODRST),
RSTMGR_PER0MODRST_EMAC0 |
RSTMGR_PER0MODRST_EMAC1 |
RSTMGR_PER0MODRST_EMAC2);
mmio_clrsetbits_32(SOCFPGA_SYSMGR(EMAC_0),
PHY_INTF_SEL_MSK, EMAC0_PHY_MODE);
mmio_clrsetbits_32(SOCFPGA_SYSMGR(EMAC_1),
PHY_INTF_SEL_MSK, EMAC1_PHY_MODE);
mmio_clrsetbits_32(SOCFPGA_SYSMGR(EMAC_2),
PHY_INTF_SEL_MSK, EMAC2_PHY_MODE);
mmio_clrbits_32(SOCFPGA_SYSMGR(FPGAINTF_EN_3),
FPGAINTF_EN_3_EMAC_MSK(0) |
FPGAINTF_EN_3_EMAC_MSK(1) |
FPGAINTF_EN_3_EMAC_MSK(2));
mmio_clrbits_32(SOCFPGA_RSTMGR(PER0MODRST),
RSTMGR_PER0MODRST_EMAC0 |
RSTMGR_PER0MODRST_EMAC1 |
RSTMGR_PER0MODRST_EMAC2);
}

6
plat/intel/soc/stratix10/bl2_plat_setup.c
View File

@ -1,6 +1,6 @@
/*
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2019, Intel Corporation. All rights reserved.
* Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -16,6 +16,7 @@
#include <lib/xlat_tables/xlat_tables.h>
#include "qspi/cadence_qspi.h"
#include "socfpga_emac.h"
#include "socfpga_handoff.h"
#include "socfpga_mailbox.h"
#include "socfpga_private.h"
@ -69,6 +70,7 @@ void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1,
console_16550_register(PLAT_UART0_BASE, get_uart_clk(), PLAT_BAUDRATE,
&console);
socfpga_emac_init();
socfpga_delay_timer_init();
init_hard_memory_controller();
mailbox_init();

5
plat/intel/soc/stratix10/platform.mk
View File

@ -1,6 +1,6 @@
#
# Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
# Copyright (c) 2019, Intel Corporation. All rights reserved.
# Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
# Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@ -42,6 +42,7 @@ BL2_SOURCES += \
plat/intel/soc/common/socfpga_delay_timer.c \
plat/intel/soc/common/socfpga_image_load.c \
plat/intel/soc/common/socfpga_storage.c \
plat/intel/soc/common/soc/socfpga_emac.c \
plat/intel/soc/common/soc/socfpga_handoff.c \
plat/intel/soc/common/soc/socfpga_mailbox.c \
plat/intel/soc/common/soc/socfpga_reset_manager.c \

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