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Currently the EL2 part of the context structure (el2_sysregs_t), is mostly feature dependent. For instance, CTX_HCRX_EL2 is only needed when FEAT_HCX (ENABLE_FEAT_HCX=1) is set, but the entry is unconditionally added in the EL2 context structure and thereby consuming memory even in build configurations where FEAT_HCX is disabled. Henceforth, all such context entries should be coupled/tied with their respective feature enables and be optimized away when unused. This would reduce the context memory allocation for platforms, that dont enable/support all the architectural features at once. Further, converting the assembly context-offset entries into a c structure relies on garbage collection of the linker removing unreferenced structures from memory, as well as aiding in readability and future maintenance. Change-Id: I0cf49498ee3033cb6f3ee3810331121b26627783 Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>pull/2000/merge
Jayanth Dodderi Chidanand
10 months ago
6 changed files with 526 additions and 289 deletions
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/*
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* Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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#ifndef CONTEXT_EL2_H |
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#define CONTEXT_EL2_H |
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#ifndef __ASSEMBLER__ |
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/*******************************************************************************
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* EL2 Registers: |
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* AArch64 EL2 system register context structure for preserving the |
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* architectural state during world switches. |
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******************************************************************************/ |
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#if CTX_INCLUDE_EL2_REGS |
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typedef struct el2_common_regs { |
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uint64_t actlr_el2; |
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uint64_t afsr0_el2; |
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uint64_t afsr1_el2; |
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uint64_t amair_el2; |
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uint64_t cnthctl_el2; |
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uint64_t cntvoff_el2; |
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uint64_t cptr_el2; |
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uint64_t dbgvcr32_el2; |
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uint64_t elr_el2; |
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uint64_t esr_el2; |
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uint64_t far_el2; |
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uint64_t hacr_el2; |
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uint64_t hcr_el2; |
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uint64_t hpfar_el2; |
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uint64_t hstr_el2; |
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uint64_t icc_sre_el2; |
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uint64_t ich_hcr_el2; |
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uint64_t ich_vmcr_el2; |
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uint64_t mair_el2; |
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uint64_t mdcr_el2; |
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uint64_t pmscr_el2; |
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uint64_t sctlr_el2; |
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uint64_t spsr_el2; |
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uint64_t sp_el2; |
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uint64_t tcr_el2; |
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uint64_t tpidr_el2; |
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uint64_t ttbr0_el2; |
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uint64_t vbar_el2; |
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uint64_t vmpidr_el2; |
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uint64_t vpidr_el2; |
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uint64_t vtcr_el2; |
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uint64_t vttbr_el2; |
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} el2_common_regs_t; |
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typedef struct el2_mte_regs { |
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uint64_t tfsr_el2; |
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} el2_mte_regs_t; |
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typedef struct el2_fgt_regs { |
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uint64_t hdfgrtr_el2; |
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uint64_t hafgrtr_el2; |
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uint64_t hdfgwtr_el2; |
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uint64_t hfgitr_el2; |
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uint64_t hfgrtr_el2; |
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uint64_t hfgwtr_el2; |
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} el2_fgt_regs_t; |
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typedef struct el2_ecv_regs { |
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uint64_t cntpoff_el2; |
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} el2_ecv_regs_t; |
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typedef struct el2_vhe_regs { |
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uint64_t contextidr_el2; |
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uint64_t ttbr1_el2; |
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} el2_vhe_regs_t; |
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typedef struct el2_ras_regs { |
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uint64_t vdisr_el2; |
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uint64_t vsesr_el2; |
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} el2_ras_regs_t; |
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typedef struct el2_neve_regs { |
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uint64_t vncr_el2; |
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} el2_neve_regs_t; |
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typedef struct el2_trf_regs { |
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uint64_t trfcr_el2; |
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} el2_trf_regs_t; |
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typedef struct el2_csv2_regs { |
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uint64_t scxtnum_el2; |
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} el2_csv2_regs_t; |
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typedef struct el2_hcx_regs { |
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uint64_t hcrx_el2; |
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} el2_hcx_regs_t; |
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typedef struct el2_tcr2_regs { |
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uint64_t tcr2_el2; |
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} el2_tcr2_regs_t; |
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typedef struct el2_sxpoe_regs { |
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uint64_t por_el2; |
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} el2_sxpoe_regs_t; |
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typedef struct el2_sxpie_regs { |
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uint64_t pire0_el2; |
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uint64_t pir_el2; |
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} el2_sxpie_regs_t; |
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typedef struct el2_s2pie_regs { |
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uint64_t s2pir_el2; |
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} el2_s2pie_regs_t; |
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typedef struct el2_gcs_regs { |
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uint64_t gcscr_el2; |
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uint64_t gcspr_el2; |
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} el2_gcs_regs_t; |
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typedef struct el2_sysregs { |
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el2_common_regs_t common; |
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#if ENABLE_FEAT_MTE |
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el2_mte_regs_t mte; |
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#endif |
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#if ENABLE_FEAT_FGT |
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el2_fgt_regs_t fgt; |
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#endif |
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#if ENABLE_FEAT_ECV |
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el2_ecv_regs_t ecv; |
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#endif |
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#if ENABLE_FEAT_VHE |
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el2_vhe_regs_t vhe; |
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#endif |
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#if ENABLE_FEAT_RAS |
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el2_ras_regs_t ras; |
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#endif |
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#if CTX_INCLUDE_NEVE_REGS |
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el2_neve_regs_t neve; |
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#endif |
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#if ENABLE_TRF_FOR_NS |
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el2_trf_regs_t trf; |
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#endif |
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#if ENABLE_FEAT_CSV2_2 |
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el2_csv2_regs_t csv2; |
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#endif |
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#if ENABLE_FEAT_HCX |
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el2_hcx_regs_t hcx; |
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#endif |
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#if ENABLE_FEAT_TCR2 |
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el2_tcr2_regs_t tcr2; |
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#endif |
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#if (ENABLE_FEAT_S1POE || ENABLE_FEAT_S2POE) |
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el2_sxpoe_regs_t sxpoe; |
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#endif |
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#if (ENABLE_FEAT_S1PIE || ENABLE_FEAT_S2PIE) |
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el2_sxpie_regs_t sxpie; |
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#endif |
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#if ENABLE_FEAT_S2PIE |
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el2_s2pie_regs_t s2pie; |
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#endif |
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#if ENABLE_FEAT_GCS |
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el2_gcs_regs_t gcs; |
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#endif |
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} el2_sysregs_t; |
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/*
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* Macros to access members related to individual features of the el2_sysregs_t |
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* structures. |
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*/ |
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#define read_el2_ctx_common(ctx, reg) (((ctx)->common).reg) |
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#define write_el2_ctx_common(ctx, reg, val) ((((ctx)->common).reg) \ |
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= (uint64_t) (val)) |
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#if ENABLE_FEAT_MTE |
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#define read_el2_ctx_mte(ctx, reg) (((ctx)->mte).reg) |
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#define write_el2_ctx_mte(ctx, reg, val) ((((ctx)->mte).reg) \ |
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= (uint64_t) (val)) |
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#else |
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#define read_el2_ctx_mte(ctx, reg) ULL(0) |
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#define write_el2_ctx_mte(ctx, reg, val) |
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#endif /* ENABLE_FEAT_MTE */ |
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#if ENABLE_FEAT_FGT |
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#define read_el2_ctx_fgt(ctx, reg) (((ctx)->fgt).reg) |
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#define write_el2_ctx_fgt(ctx, reg, val) ((((ctx)->fgt).reg) \ |
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= (uint64_t) (val)) |
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#else |
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#define read_el2_ctx_fgt(ctx, reg) ULL(0) |
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#define write_el2_ctx_fgt(ctx, reg, val) |
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#endif /* ENABLE_FEAT_FGT */ |
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#if ENABLE_FEAT_ECV |
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#define read_el2_ctx_ecv(ctx, reg) (((ctx)->ecv).reg) |
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#define write_el2_ctx_ecv(ctx, reg, val) ((((ctx)->ecv).reg) \ |
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= (uint64_t) (val)) |
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#else |
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#define read_el2_ctx_ecv(ctx, reg) ULL(0) |
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#define write_el2_ctx_ecv(ctx, reg, val) |
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#endif /* ENABLE_FEAT_ECV */ |
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#if ENABLE_FEAT_VHE |
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#define read_el2_ctx_vhe(ctx, reg) (((ctx)->vhe).reg) |
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#define write_el2_ctx_vhe(ctx, reg, val) ((((ctx)->vhe).reg) \ |
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= (uint64_t) (val)) |
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#else |
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#define read_el2_ctx_vhe(ctx, reg) ULL(0) |
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#define write_el2_ctx_vhe(ctx, reg, val) |
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#endif /* ENABLE_FEAT_VHE */ |
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#if ENABLE_FEAT_RAS |
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#define read_el2_ctx_ras(ctx, reg) (((ctx)->ras).reg) |
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#define write_el2_ctx_ras(ctx, reg, val) ((((ctx)->ras).reg) \ |
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= (uint64_t) (val)) |
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#else |
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#define read_el2_ctx_ras(ctx, reg) ULL(0) |
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#define write_el2_ctx_ras(ctx, reg, val) |
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#endif /* ENABLE_FEAT_RAS */ |
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#if CTX_INCLUDE_NEVE_REGS |
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#define read_el2_ctx_neve(ctx, reg) (((ctx)->neve).reg) |
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#define write_el2_ctx_neve(ctx, reg, val) ((((ctx)->neve).reg) \ |
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= (uint64_t) (val)) |
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#else |
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#define read_el2_ctx_neve(ctx, reg) ULL(0) |
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#define write_el2_ctx_neve(ctx, reg, val) |
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#endif /* CTX_INCLUDE_NEVE_REGS */ |
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#if ENABLE_TRF_FOR_NS |
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#define read_el2_ctx_trf(ctx, reg) (((ctx)->trf).reg) |
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#define write_el2_ctx_trf(ctx, reg, val) ((((ctx)->trf).reg) \ |
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= (uint64_t) (val)) |
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#else |
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#define read_el2_ctx_trf(ctx, reg) ULL(0) |
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#define write_el2_ctx_trf(ctx, reg, val) |
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#endif /* ENABLE_TRF_FOR_NS */ |
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#if ENABLE_FEAT_CSV2_2 |
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#define read_el2_ctx_csv2_2(ctx, reg) (((ctx)->csv2).reg) |
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#define write_el2_ctx_csv2_2(ctx, reg, val) ((((ctx)->csv2).reg) \ |
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= (uint64_t) (val)) |
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#else |
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#define read_el2_ctx_csv2_2(ctx, reg) ULL(0) |
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#define write_el2_ctx_csv2_2(ctx, reg, val) |
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#endif /* ENABLE_FEAT_CSV2_2 */ |
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#if ENABLE_FEAT_HCX |
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#define read_el2_ctx_hcx(ctx, reg) (((ctx)->hcx).reg) |
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#define write_el2_ctx_hcx(ctx, reg, val) ((((ctx)->hcx).reg) \ |
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= (uint64_t) (val)) |
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#else |
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#define read_el2_ctx_hcx(ctx, reg) ULL(0) |
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#define write_el2_ctx_hcx(ctx, reg, val) |
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#endif /* ENABLE_FEAT_HCX */ |
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#if ENABLE_FEAT_TCR2 |
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#define read_el2_ctx_tcr2(ctx, reg) (((ctx)->tcr2).reg) |
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#define write_el2_ctx_tcr2(ctx, reg, val) ((((ctx)->tcr2).reg) \ |
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= (uint64_t) (val)) |
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#else |
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#define read_el2_ctx_tcr2(ctx, reg) ULL(0) |
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#define write_el2_ctx_tcr2(ctx, reg, val) |
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#endif /* ENABLE_FEAT_TCR2 */ |
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#if (ENABLE_FEAT_S1POE || ENABLE_FEAT_S2POE) |
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#define read_el2_ctx_sxpoe(ctx, reg) (((ctx)->sxpoe).reg) |
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#define write_el2_ctx_sxpoe(ctx, reg, val) ((((ctx)->sxpoe).reg) \ |
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= (uint64_t) (val)) |
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#else |
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#define read_el2_ctx_sxpoe(ctx, reg) ULL(0) |
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#define write_el2_ctx_sxpoe(ctx, reg, val) |
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#endif /*(ENABLE_FEAT_S1POE || ENABLE_FEAT_S2POE) */ |
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#if (ENABLE_FEAT_S1PIE || ENABLE_FEAT_S2PIE) |
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#define read_el2_ctx_sxpie(ctx, reg) (((ctx)->sxpie).reg) |
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#define write_el2_ctx_sxpie(ctx, reg, val) ((((ctx)->sxpie).reg) \ |
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= (uint64_t) (val)) |
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#else |
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#define read_el2_ctx_sxpie(ctx, reg) ULL(0) |
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#define write_el2_ctx_sxpie(ctx, reg, val) |
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#endif /*(ENABLE_FEAT_S1PIE || ENABLE_FEAT_S2PIE) */ |
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#if ENABLE_FEAT_S2PIE |
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#define read_el2_ctx_s2pie(ctx, reg) (((ctx)->s2pie).reg) |
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#define write_el2_ctx_s2pie(ctx, reg, val) ((((ctx)->s2pie).reg) \ |
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= (uint64_t) (val)) |
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#else |
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#define read_el2_ctx_s2pie(ctx, reg) ULL(0) |
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#define write_el2_ctx_s2pie(ctx, reg, val) |
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#endif /* ENABLE_FEAT_S2PIE */ |
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#if ENABLE_FEAT_GCS |
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#define read_el2_ctx_gcs(ctx, reg) (((ctx)->gcs).reg) |
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#define write_el2_ctx_gcs(ctx, reg, val) ((((ctx)->gcs).reg) \ |
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= (uint64_t) (val)) |
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#else |
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#define read_el2_ctx_gcs(ctx, reg) ULL(0) |
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#define write_el2_ctx_gcs(ctx, reg, val) |
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#endif /* ENABLE_FEAT_GCS */ |
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#endif /* CTX_INCLUDE_EL2_REGS */ |
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/******************************************************************************/ |
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#endif /* __ASSEMBLER__ */ |
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#endif /* CONTEXT_EL2_H */ |
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