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TZMP1 protected memory regions have been added in the Juno platform to store sensitive data for the Arm(R) Ethos(TM)-N NPU This is enabled when building TF-A with ARM_ETHOSN_NPU_TZMP1. The NPU uses two protected memory regions: 1) Firmware region to protect the NPU's firmware from being modified from the non-secure world 2) Data region for sensitive data used by the NPU Respective memory region can only be accessed with their unique NSAID. Signed-off-by: Bjorn Engstrom <bjoern.engstroem@arm.com> Signed-off-by: Mikael Olsson <mikael.olsson@arm.com> Signed-off-by: Rob Hughes <robert.hughes@arm.com> Change-Id: I65200047f10364ca18681ce348a6edb2ffb9b095pull/1996/head
Bjorn Engstrom
2 years ago
committed by
Joanna Farley
2 changed files with 63 additions and 6 deletions
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/*
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* Copyright (c) 2023, Arm Limited. All rights reserved. |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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#ifndef JUNO_ETHOSN_TZMP1_DEF_H |
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#define JUNO_ETHOSN_TZMP1_DEF_H |
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#define JUNO_ETHOSN_TZC400_NSAID_FW_PROT 7 |
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#define JUNO_ETHOSN_TZC400_NSAID_DATA_PROT 8 |
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#define JUNO_ETHOSN_FW_TZC_PROT_DRAM2_SIZE UL(0x000400000) /* 4 MB */ |
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#define JUNO_ETHOSN_FW_TZC_PROT_DRAM2_BASE (ARM_DRAM2_BASE) |
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#define JUNO_ETHOSN_FW_TZC_PROT_DRAM2_END (ARM_DRAM2_BASE + \ |
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JUNO_ETHOSN_FW_TZC_PROT_DRAM2_SIZE \ |
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- 1U) |
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#define JUNO_ETHOSN_DATA_TZC_PROT_DRAM2_SIZE UL(0x004000000) /* 64 MB */ |
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#define JUNO_ETHOSN_DATA_TZC_PROT_DRAM2_BASE ( \ |
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JUNO_ETHOSN_FW_TZC_PROT_DRAM2_END + 1) |
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#define JUNO_ETHOSN_DATA_TZC_PROT_DRAM2_END ( \ |
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JUNO_ETHOSN_DATA_TZC_PROT_DRAM2_BASE + \ |
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JUNO_ETHOSN_DATA_TZC_PROT_DRAM2_SIZE - 1U) |
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#define JUNO_ETHOSN_NS_DRAM2_BASE (JUNO_ETHOSN_DATA_TZC_PROT_DRAM2_END + \ |
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1) |
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#define JUNO_ETHOSN_NS_DRAM2_END (ARM_DRAM2_END) |
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#define JUNO_ETHOSN_NS_DRAM2_SIZE (ARM_DRAM2_SIZE - \ |
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JUNO_ETHOSN_DATA_TZC_PROT_DRAM2_END) |
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#define JUNO_FW_TZC_PROT_ACCESS \ |
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(TZC_REGION_ACCESS_RDWR(JUNO_ETHOSN_TZC400_NSAID_FW_PROT)) |
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#define JUNO_DATA_TZC_PROT_ACCESS \ |
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(TZC_REGION_ACCESS_RDWR(JUNO_ETHOSN_TZC400_NSAID_DATA_PROT)) |
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#define JUNO_ETHOSN_TZMP_REGIONS_DEF \ |
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{ ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END + ARM_L1_GPT_SIZE, \ |
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TZC_REGION_S_RDWR, 0 }, \ |
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{ ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, \ |
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ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS }, \ |
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{ JUNO_ETHOSN_FW_TZC_PROT_DRAM2_BASE, \ |
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JUNO_ETHOSN_FW_TZC_PROT_DRAM2_END, \ |
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TZC_REGION_S_RDWR, JUNO_FW_TZC_PROT_ACCESS }, \ |
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{ JUNO_ETHOSN_DATA_TZC_PROT_DRAM2_BASE, \ |
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JUNO_ETHOSN_DATA_TZC_PROT_DRAM2_END, \ |
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TZC_REGION_S_NONE, JUNO_DATA_TZC_PROT_ACCESS }, \ |
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{ JUNO_ETHOSN_NS_DRAM2_BASE, JUNO_ETHOSN_NS_DRAM2_END, \ |
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ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS } |
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#endif /* JUNO_ETHOSN_TZMP1_DEF_H */ |
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