From d91d10ab39b29339f1c98d95745ba98476fd7e46 Mon Sep 17 00:00:00 2001 From: Lionel Debieve Date: Thu, 12 Nov 2020 10:44:51 +0100 Subject: [PATCH] feat(st-reset): add system reset management Add the system reset management into the stm32mp reset driver. Signed-off-by: Lionel Debieve Change-Id: I748f10de2398e1323160f479f99e92abd2f65dca --- drivers/st/reset/stm32mp1_reset.c | 19 ++++++++++++++++--- include/drivers/st/stm32mp_reset.h | 7 ++++++- plat/st/stm32mp1/stm32mp1_pm.c | 11 +++-------- 3 files changed, 25 insertions(+), 12 deletions(-) diff --git a/drivers/st/reset/stm32mp1_reset.c b/drivers/st/reset/stm32mp1_reset.c index 98c8dcf71..8b828a15c 100644 --- a/drivers/st/reset/stm32mp1_reset.c +++ b/drivers/st/reset/stm32mp1_reset.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, STMicroelectronics - All Rights Reserved + * Copyright (c) 2018-2024, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,8 +7,6 @@ #include #include -#include - #include #include #include @@ -16,6 +14,8 @@ #include #include +#include + static uint32_t id2reg_offset(unsigned int reset_id) { return ((reset_id & GENMASK(31, 5)) >> 5) * sizeof(uint32_t); @@ -67,3 +67,16 @@ int stm32mp_reset_deassert(uint32_t id, unsigned int to_us) return 0; } + +void __dead2 stm32mp_system_reset(void) +{ + uintptr_t rcc_base = stm32mp_rcc_base(); + + mmio_setbits_32(rcc_base + RCC_MP_GRSTCSETR, + RCC_MP_GRSTCSETR_MPSYSRST); + + /* Loop in case system reset is not immediately caught */ + while (true) { + wfi(); + } +} diff --git a/include/drivers/st/stm32mp_reset.h b/include/drivers/st/stm32mp_reset.h index 84448050d..a8648b43e 100644 --- a/include/drivers/st/stm32mp_reset.h +++ b/include/drivers/st/stm32mp_reset.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, STMicroelectronics - All Rights Reserved + * Copyright (c) 2018-2024, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -47,4 +47,9 @@ static inline void stm32mp_reset_release(uint32_t reset_id) (void)stm32mp_reset_deassert(reset_id, 0U); } +/* + * Manage system reset control + */ +void __dead2 stm32mp_system_reset(void); + #endif /* STM32MP_RESET_H */ diff --git a/plat/st/stm32mp1/stm32mp1_pm.c b/plat/st/stm32mp1/stm32mp1_pm.c index ff2218fd3..97e1ac61b 100644 --- a/plat/st/stm32mp1/stm32mp1_pm.c +++ b/plat/st/stm32mp1/stm32mp1_pm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -149,13 +150,7 @@ static void __dead2 stm32_system_off(void) static void __dead2 stm32_system_reset(void) { - mmio_setbits_32(stm32mp_rcc_base() + RCC_MP_GRSTCSETR, - RCC_MP_GRSTCSETR_MPSYSRST); - - /* Loop in case system reset is not immediately caught */ - for ( ; ; ) { - ; - } + stm32mp_system_reset(); } static int stm32_validate_power_state(unsigned int power_state,