From da7a33cf2f27545d9d290ff0c2ee1ec333b061bb Mon Sep 17 00:00:00 2001 From: Christophe Kerello Date: Tue, 27 Sep 2022 11:02:55 +0200 Subject: [PATCH] fix(spi-nand): add Quad Enable management The framework currently supports QE feature only for Macronix devices. Kioxia devices also support this feature, but this feature can not be set based on the manufacturer ID as Kioxia first SPI NAND generation does not support the QE feature when the second generation does. Use a flag to manage QE feature. This flag will be added at board level to manage the device. Change-Id: I7a3683a2df8739967b17b4abbec32c51bf206b93 Signed-off-by: Christophe Kerello --- drivers/mtd/nand/spi_nand.c | 5 ++--- include/drivers/spi_nand.h | 6 +++++- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/nand/spi_nand.c b/drivers/mtd/nand/spi_nand.c index 542b614ff..744383aa3 100644 --- a/drivers/mtd/nand/spi_nand.c +++ b/drivers/mtd/nand/spi_nand.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2022, STMicroelectronics - All Rights Reserved + * Copyright (c) 2019-2023, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,7 +17,6 @@ #define SPI_NAND_MAX_ID_LEN 4U #define DELAY_US_400MS 400000U -#define MACRONIX_ID 0xC2U static struct spinand_device spinand_dev; @@ -91,7 +90,7 @@ static int spi_nand_quad_enable(uint8_t manufacturer_id) { bool enable = false; - if (manufacturer_id != MACRONIX_ID) { + if ((spinand_dev.flags & SPI_NAND_HAS_QE_BIT) == 0U) { return 0; } diff --git a/include/drivers/spi_nand.h b/include/drivers/spi_nand.h index 40e206375..869a0c689 100644 --- a/include/drivers/spi_nand.h +++ b/include/drivers/spi_nand.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, STMicroelectronics - All Rights Reserved + * Copyright (c) 2019-2023, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -29,9 +29,13 @@ #define SPI_NAND_STATUS_BUSY BIT(0) #define SPI_NAND_STATUS_ECC_UNCOR BIT(5) +/* Flags for specific configuration */ +#define SPI_NAND_HAS_QE_BIT BIT(0) + struct spinand_device { struct nand_device *nand_dev; struct spi_mem_op spi_read_cache_op; + uint32_t flags; uint8_t cfg_cache; /* Cached value of SPI NAND device register CFG */ };