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This change adds optional reset vector support to BL3-1 which means BL3-1 entry point can detect cold/warm boot, initialise primary cpu, set up cci and mail box. When using BL3-1 as a reset vector it is assumed that the BL3-1 platform code can determine the location of the BL3-2 images, or load them as there are no parameters that can be passed to BL3-1 at reset. It also fixes the incorrect initialisation of mailbox registers on the FVP platform This feature can be enabled by building the code with make variable RESET_TO_BL31 set as 1 Fixes ARM-software/TF-issues#133 Fixes ARM-software/TF-issues#20 Change-Id: I4e23939b1c518614b899f549f1e8d412538ee570pull/99/head
Vikram Kanigiri
11 years ago
14 changed files with 404 additions and 305 deletions
@ -1,213 +0,0 @@ |
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/* |
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* Redistributions of source code must retain the above copyright notice, this |
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* list of conditions and the following disclaimer. |
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* |
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* Redistributions in binary form must reproduce the above copyright notice, |
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* this list of conditions and the following disclaimer in the documentation |
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* and/or other materials provided with the distribution. |
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* |
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* Neither the name of ARM nor the names of its contributors may be used |
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* to endorse or promote products derived from this software without specific |
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* prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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* POSSIBILITY OF SUCH DAMAGE. |
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*/ |
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#include <arch.h> |
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#include <asm_macros.S> |
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#include <gic_v2.h> |
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#include <platform.h> |
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#include "../drivers/pwrc/fvp_pwrc.h" |
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.globl platform_get_entrypoint |
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.globl platform_cold_boot_init |
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.globl plat_secondary_cold_boot_setup |
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.macro platform_choose_gicmmap param1, param2, x_tmp, w_tmp, res |
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ldr \x_tmp, =VE_SYSREGS_BASE + V2M_SYS_ID |
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ldr \w_tmp, [\x_tmp] |
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ubfx \w_tmp, \w_tmp, #SYS_ID_BLD_SHIFT, #SYS_ID_BLD_LENGTH |
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cmp \w_tmp, #BLD_GIC_VE_MMAP |
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csel \res, \param1, \param2, eq |
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.endm |
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/* ----------------------------------------------------- |
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* void plat_secondary_cold_boot_setup (void); |
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* |
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* This function performs any platform specific actions |
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* needed for a secondary cpu after a cold reset e.g |
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* mark the cpu's presence, mechanism to place it in a |
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* holding pen etc. |
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* TODO: Should we read the PSYS register to make sure |
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* that the request has gone through. |
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* ----------------------------------------------------- |
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*/ |
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func plat_secondary_cold_boot_setup |
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/* --------------------------------------------- |
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* Power down this cpu. |
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* TODO: Do we need to worry about powering the |
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* cluster down as well here. That will need |
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* locks which we won't have unless an elf- |
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* loader zeroes out the zi section. |
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* --------------------------------------------- |
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*/ |
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mrs x0, mpidr_el1 |
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ldr x1, =PWRC_BASE |
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str w0, [x1, #PPOFFR_OFF] |
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/* --------------------------------------------- |
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* Deactivate the gic cpu interface as well |
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* --------------------------------------------- |
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*/ |
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ldr x0, =VE_GICC_BASE |
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ldr x1, =BASE_GICC_BASE |
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platform_choose_gicmmap x0, x1, x2, w2, x1 |
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mov w0, #(IRQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP1) |
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orr w0, w0, #(IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP0) |
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str w0, [x1, #GICC_CTLR] |
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/* --------------------------------------------- |
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* There is no sane reason to come out of this |
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* wfi so panic if we do. This cpu will be pow- |
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* ered on and reset by the cpu_on pm api |
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* --------------------------------------------- |
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*/ |
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dsb sy |
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wfi |
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cb_panic: |
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b cb_panic |
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/* ----------------------------------------------------- |
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* void platform_get_entrypoint (unsigned int mpid); |
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* |
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* Main job of this routine is to distinguish between |
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* a cold and warm boot. |
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* On a cold boot the secondaries first wait for the |
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* platform to be initialized after which they are |
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* hotplugged in. The primary proceeds to perform the |
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* platform initialization. |
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* On a warm boot, each cpu jumps to the address in its |
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* mailbox. |
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* |
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* TODO: Not a good idea to save lr in a temp reg |
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* TODO: PSYSR is a common register and should be |
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* accessed using locks. Since its not possible |
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* to use locks immediately after a cold reset |
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* we are relying on the fact that after a cold |
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* reset all cpus will read the same WK field |
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* ----------------------------------------------------- |
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*/ |
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func platform_get_entrypoint |
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mov x9, x30 // lr |
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mov x2, x0 |
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ldr x1, =PWRC_BASE |
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str w2, [x1, #PSYSR_OFF] |
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ldr w2, [x1, #PSYSR_OFF] |
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ubfx w2, w2, #PSYSR_WK_SHIFT, #PSYSR_WK_MASK |
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cbnz w2, warm_reset |
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mov x0, x2 |
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b exit |
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warm_reset: |
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/* --------------------------------------------- |
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* A per-cpu mailbox is maintained in the tru- |
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* sted DRAM. Its flushed out of the caches |
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* after every update using normal memory so |
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* its safe to read it here with SO attributes |
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* --------------------------------------------- |
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*/ |
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ldr x10, =TZDRAM_BASE + MBOX_OFF |
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bl platform_get_core_pos |
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lsl x0, x0, #CACHE_WRITEBACK_SHIFT |
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ldr x0, [x10, x0] |
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cbz x0, _panic |
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exit: |
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ret x9 |
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_panic: b _panic |
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/* ----------------------------------------------------- |
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* void platform_mem_init (void); |
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* |
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* Zero out the mailbox registers in the TZDRAM. The |
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* mmu is turned off right now and only the primary can |
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* ever execute this code. Secondaries will read the |
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* mailboxes using SO accesses. In short, BL31 will |
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* update the mailboxes after mapping the tzdram as |
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* normal memory. It will flush its copy after update. |
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* BL1 will always read the mailboxes with the MMU off |
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* ----------------------------------------------------- |
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*/ |
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func platform_mem_init |
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ldr x0, =TZDRAM_BASE + MBOX_OFF |
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stp xzr, xzr, [x0, #0] |
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stp xzr, xzr, [x0, #0x10] |
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stp xzr, xzr, [x0, #0x20] |
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stp xzr, xzr, [x0, #0x30] |
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ret |
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/* ----------------------------------------------------- |
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* void platform_cold_boot_init (bl1_main function); |
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* |
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* Routine called only by the primary cpu after a cold |
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* boot to perform early platform initialization |
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* ----------------------------------------------------- |
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*/ |
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func platform_cold_boot_init |
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mov x20, x0 |
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bl platform_mem_init |
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/* --------------------------------------------- |
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* Give ourselves a small coherent stack to |
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* ease the pain of initializing the MMU and |
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* CCI in assembler |
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* --------------------------------------------- |
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*/ |
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mrs x0, mpidr_el1 |
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bl platform_set_coherent_stack |
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/* --------------------------------------------- |
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* Architectural init. can be generic e.g. |
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* enabling stack alignment and platform spec- |
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* ific e.g. MMU & page table setup as per the |
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* platform memory map. Perform the latter here |
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* and the former in bl1_main. |
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* --------------------------------------------- |
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*/ |
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bl bl1_early_platform_setup |
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bl bl1_plat_arch_setup |
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/* --------------------------------------------- |
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* Give ourselves a stack allocated in Normal |
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* -IS-WBWA memory |
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* --------------------------------------------- |
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*/ |
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mrs x0, mpidr_el1 |
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bl platform_set_stack |
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/* --------------------------------------------- |
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* Jump to the main function. Returning from it |
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* is a terminal error. |
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* --------------------------------------------- |
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*/ |
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blr x20 |
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cb_init_panic: |
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b cb_init_panic |
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