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@ -988,27 +988,27 @@ static void __clk_enable(struct stm32mp1_clk_gate const *gate) |
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{ |
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uintptr_t rcc_base = stm32mp_rcc_base(); |
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VERBOSE("Enable clock %u\n", gate->index); |
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if (gate->set_clr != 0U) { |
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mmio_write_32(rcc_base + gate->offset, BIT(gate->bit)); |
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} else { |
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mmio_setbits_32(rcc_base + gate->offset, BIT(gate->bit)); |
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} |
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VERBOSE("Clock %d has been enabled", gate->index); |
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} |
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static void __clk_disable(struct stm32mp1_clk_gate const *gate) |
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{ |
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uintptr_t rcc_base = stm32mp_rcc_base(); |
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VERBOSE("Disable clock %u\n", gate->index); |
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if (gate->set_clr != 0U) { |
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mmio_write_32(rcc_base + gate->offset + RCC_MP_ENCLRR_OFFSET, |
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BIT(gate->bit)); |
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} else { |
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mmio_clrbits_32(rcc_base + gate->offset, BIT(gate->bit)); |
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} |
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VERBOSE("Clock %d has been disabled", gate->index); |
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} |
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static bool __clk_is_enabled(struct stm32mp1_clk_gate const *gate) |
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