feat(tc): enable el1 access to DSU PMU registers

DSU PMU registers are write accessible in EL1 if the ACTLR_EL3[12] bit
and the ACTLR_EL2[12] bit are set to 1, and these registers are need to
be set for all cores, so set these bits in platform reset handler.

Change-Id: I1db6915939727f0909c05c8b103e37984aadb443
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

plat/arm/board/tc/include/platform_def.h

@@ -448,4 +448,6 @@
 #define SLC_ALLOC_BUS_SIGNAL_ATTR	2
 #endif /* TARGET_PLATFORM == 3 */
 
+#define CPUACTLR_CLUSTERPMUEN		(ULL(1) << 12)
+
 #endif /* PLATFORM_DEF_H */

plat/arm/board/tc/include/tc_helpers.S

@@ -9,6 +9,9 @@
 #include <platform_def.h>
 #include <cpu_macros.S>
 
+#define TC_HANDLER(rev)         plat_reset_handler_tc##rev
+#define PLAT_RESET_HANDLER(rev) TC_HANDLER(rev)
+
 	.globl	plat_arm_calc_core_pos
 	.globl	plat_reset_handler
 
@@ -49,10 +52,30 @@ func plat_arm_calc_core_pos
 	ret
 endfunc plat_arm_calc_core_pos
 
+func enable_dsu_pmu_el1_access
+	sysreg_bit_set actlr_el2, CPUACTLR_CLUSTERPMUEN
+	sysreg_bit_set actlr_el3, CPUACTLR_CLUSTERPMUEN
+	ret
+endfunc enable_dsu_pmu_el1_access
+
+func TC_HANDLER(2)
+	ret
+endfunc TC_HANDLER(2)
+
+func TC_HANDLER(3)
+	mov	x9, lr
+	bl	enable_dsu_pmu_el1_access
+	mov	lr, x9
+	ret
+endfunc TC_HANDLER(3)
+
 	/* -----------------------------------------------------
 	 * void plat_reset_handler(void);
 	 * -----------------------------------------------------
 	 */
 func plat_reset_handler
+	mov	x8, lr
+	bl	PLAT_RESET_HANDLER(TARGET_PLATFORM)
+	mov	lr, x8
 	ret
 endfunc plat_reset_handler