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@ -29,9 +29,8 @@ int psci_cpu_on(u_register_t target_cpu, |
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int rc; |
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entry_point_info_t ep; |
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/* Determine if the cpu exists of not */ |
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rc = psci_validate_mpidr(target_cpu); |
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if (rc != PSCI_E_SUCCESS) |
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/* Validate the target CPU */ |
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if (!is_valid_mpidr(target_cpu)) |
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return PSCI_E_INVALID_PARAMS; |
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/* Validate the entry point and get the entry_point_info */ |
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@ -245,19 +244,18 @@ int psci_cpu_off(void) |
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int psci_affinity_info(u_register_t target_affinity, |
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unsigned int lowest_affinity_level) |
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{ |
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int ret; |
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unsigned int target_idx; |
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/* Validate the target affinity */ |
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if (!is_valid_mpidr(target_affinity)) |
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return PSCI_E_INVALID_PARAMS; |
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/* We dont support level higher than PSCI_CPU_PWR_LVL */ |
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if (lowest_affinity_level > PSCI_CPU_PWR_LVL) |
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return PSCI_E_INVALID_PARAMS; |
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/* Calculate the cpu index of the target */ |
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ret = plat_core_pos_by_mpidr(target_affinity); |
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if (ret == -1) { |
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return PSCI_E_INVALID_PARAMS; |
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} |
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target_idx = (unsigned int)ret; |
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target_idx = (unsigned int) plat_core_pos_by_mpidr(target_affinity); |
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/*
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* Generic management: |
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@ -285,6 +283,10 @@ int psci_migrate(u_register_t target_cpu) |
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int rc; |
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u_register_t resident_cpu_mpidr; |
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/* Validate the target cpu */ |
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if (!is_valid_mpidr(target_cpu)) |
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return PSCI_E_INVALID_PARAMS; |
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rc = psci_spd_migrate_info(&resident_cpu_mpidr); |
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if (rc != PSCI_TOS_UP_MIG_CAP) |
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return (rc == PSCI_TOS_NOT_UP_MIG_CAP) ? |
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@ -298,8 +300,7 @@ int psci_migrate(u_register_t target_cpu) |
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return PSCI_E_NOT_PRESENT; |
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/* Check the validity of the specified target cpu */ |
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rc = psci_validate_mpidr(target_cpu); |
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if (rc != PSCI_E_SUCCESS) |
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if (!is_valid_mpidr(target_cpu)) |
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return PSCI_E_INVALID_PARAMS; |
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assert((psci_spd_pm != NULL) && (psci_spd_pm->svc_migrate != NULL)); |
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@ -339,8 +340,7 @@ int psci_node_hw_state(u_register_t target_cpu, |
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int rc; |
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/* Validate target_cpu */ |
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rc = psci_validate_mpidr(target_cpu); |
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if (rc != PSCI_E_SUCCESS) |
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if (!is_valid_mpidr(target_cpu)) |
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return PSCI_E_INVALID_PARAMS; |
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/* Validate power_level against PLAT_MAX_PWR_LVL */ |
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