feat(tc): enable Last-level cache (LLC)

The EXTLLC bit in CPUECTLR_EL1 register indicates that an external
Last-level cache is present in the system.

This bit is not set for CPUs on TC3 platform despite there is
presence of LLC in MCN, so set them.

Change-Id: I5f889e67dce2b1d00e4ee66a8c255cf7911825b0
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

include/lib/cpus/aarch64/cortex_a520.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -15,6 +15,7 @@
 #define CORTEX_A520_CPUACTLR_EL1				S3_0_C15_C1_0
 
 #define CORTEX_A520_CPUECTLR_EL1				S3_0_C15_C1_4
+#define CORTEX_A520_CPUECTLR_EL1_EXTLLC_BIT			U(0)
 
 /*******************************************************************************
  * CPU Auxiliary Control register 1 specific definitions.

include/lib/cpus/aarch64/cortex_a725.h

@@ -13,6 +13,7 @@
  * CPU Extended Control register specific definitions
  ******************************************************************************/
 #define CORTEX_A725_CPUECTLR_EL1				S3_0_C15_C1_4
+#define CORTEX_A725_CPUECTLR_EL1_EXTLLC_BIT			U(0)
 
 /*******************************************************************************
  * CPU Power Control register specific definitions

include/lib/cpus/aarch64/cortex_x925.h

@@ -13,6 +13,7 @@
  * CPU Extended Control register specific definitions
  ******************************************************************************/
 #define CORTEX_X925_CPUECTLR_EL1				S3_0_C15_C1_4
+#define CORTEX_X925_CPUECTLR_EL1_EXTLLC_BIT			U(0)
 
 /*******************************************************************************
  * CPU Power Control register specific definitions

plat/arm/board/tc/include/platform_def.h

@@ -7,6 +7,7 @@
 #ifndef PLATFORM_DEF_H
 #define PLATFORM_DEF_H
 
+#include <cortex_a520.h>
 #include <lib/utils_def.h>
 #include <lib/xlat_tables/xlat_tables_defs.h>
 #include <plat/arm/board/common/board_css_def.h>
@@ -446,6 +447,19 @@
 #define SLC_DONT_ALLOC			0
 #define SLC_ALWAYS_ALLOC		1
 #define SLC_ALLOC_BUS_SIGNAL_ATTR	2
+
+#define MCN_CONFIG_OFFSET		0x204
+#define MCN_CONFIG_ADDR			(MCN_BASE_ADDR + MCN_CONFIG_OFFSET)
+#define MCN_CONFIG_SLC_PRESENT_BIT	3
+
+/*
+ * TC3 CPUs have the same definitions for:
+ *   CORTEX_{A520|A725|X925}_CPUECTLR_EL1
+ *   CORTEX_{A520|A725|X925}_CPUECTLR_EL1_EXTLLC_BIT
+ * Define the common macros for easier using.
+ */
+#define CPUECTLR_EL1			CORTEX_A520_CPUECTLR_EL1
+#define CPUECTLR_EL1_EXTLLC_BIT		CORTEX_A520_CPUECTLR_EL1_EXTLLC_BIT
 #endif /* TARGET_PLATFORM == 3 */
 
 #define CPUACTLR_CLUSTERPMUEN		(ULL(1) << 12)

plat/arm/board/tc/include/tc_helpers.S

@@ -52,6 +52,17 @@ func plat_arm_calc_core_pos
 	ret
 endfunc plat_arm_calc_core_pos
 
+func mark_extllc_presence
+#ifdef MCN_CONFIG_ADDR
+	mov_imm x0, (MCN_CONFIG_ADDR)
+	ldr	w1, [x0]
+	ubfx	x1, x1, #MCN_CONFIG_SLC_PRESENT_BIT, #1
+	sysreg_bitfield_insert_from_gpr CPUECTLR_EL1, x1, \
+					CPUECTLR_EL1_EXTLLC_BIT, 1
+#endif
+	ret
+endfunc mark_extllc_presence
+
 func enable_dsu_pmu_el1_access
 	sysreg_bit_set actlr_el2, CPUACTLR_CLUSTERPMUEN
 	sysreg_bit_set actlr_el3, CPUACTLR_CLUSTERPMUEN
@@ -64,6 +75,7 @@ endfunc TC_HANDLER(2)
 
 func TC_HANDLER(3)
 	mov	x9, lr
+	bl	mark_extllc_presence
 	bl	enable_dsu_pmu_el1_access
 	mov	lr, x9
 	ret