github
/
arm-trusted-firmware
mirror of https://github.com/ARM-software/arm-trusted-firmware.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
Browse Source

CPU: Make shifted constants unsigned 

In order to avoid Undefined behavior, left operand in left-shift
expressions needs to be unsigned, and of sufficient size. The safest and
most consistent approach is to use unsigned long long type.

Change-Id: I9612f16a6e6ea4c7df62a02497d862abf19b8e1b
Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com>
pull/1062/head
Eleanor Bonnici 7 years ago
committed by Jeenu Viswambharan
parent
afb33432df
commit
e4e6c4be6f
4 changed files with 63 additions and 59 deletions
Whitespace
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Split View
Diff Options
Show Stats Download Patch File Download Diff File
  1. 31
      include/lib/cpus/aarch32/cortex_a57.h
  2. 15
      include/lib/cpus/aarch32/cortex_a72.h
  3. 1
      include/lib/cpus/aarch64/cortex_a57.h
  4. 15
      include/lib/cpus/aarch64/cortex_a72.h

31
include/lib/cpus/aarch32/cortex_a57.h
View File

@ -6,6 +6,7 @@
#ifndef __CORTEX_A57_H__
#define __CORTEX_A57_H__
#include <utils_def.h>
/* Cortex-A57 midr for revision 0 */
#define CORTEX_A57_MIDR 0x410FD070
@ -24,13 +25,13 @@
******************************************************************************/
#define CORTEX_A57_ECTLR p15, 1, c15
#define CORTEX_A57_ECTLR_SMP_BIT (1 << 6)
#define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38)
#define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35)
#define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32)
#define CORTEX_A57_ECTLR_SMP_BIT (ULL(1) << 6)
#define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38)
#define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35)
#define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32)
#define CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT 0
#define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (0x7 << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT)
#define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT)
/*******************************************************************************
* CPU Memory Error Syndrome register specific definitions.
@ -42,15 +43,15 @@
******************************************************************************/
#define CORTEX_A57_ACTLR p15, 0, c15
#define CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB (1 << 59)
#define CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE (1 << 54)
#define CORTEX_A57_ACTLR_DIS_OVERREAD (1 << 52)
#define CORTEX_A57_ACTLR_NO_ALLOC_WBWA (1 << 49)
#define CORTEX_A57_ACTLR_DCC_AS_DCCI (1 << 44)
#define CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH (1 << 38)
#define CORTEX_A57_ACTLR_DIS_STREAMING (3 << 27)
#define CORTEX_A57_ACTLR_DIS_L1_STREAMING (3 << 25)
#define CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR (1 << 4)
#define CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB (ULL(1) << 59)
#define CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE (ULL(1) << 54)
#define CORTEX_A57_ACTLR_DIS_OVERREAD (ULL(1) << 52)
#define CORTEX_A57_ACTLR_NO_ALLOC_WBWA (ULL(1) << 49)
#define CORTEX_A57_ACTLR_DCC_AS_DCCI (ULL(1) << 44)
#define CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH (ULL(1) << 38)
#define CORTEX_A57_ACTLR_DIS_STREAMING (ULL(3) << 27)
#define CORTEX_A57_ACTLR_DIS_L1_STREAMING (ULL(3) << 25)
#define CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR (ULL(1) << 4)
/*******************************************************************************
* L2 Control register specific definitions.
@ -69,7 +70,7 @@
#define CORTEX_A57_L2ECTLR p15, 1, c9, c0, 3
#define CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT 0
#define CORTEX_A57_L2ECTLR_RET_CTRL_MASK (0x7 << CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT)
#define CORTEX_A57_L2ECTLR_RET_CTRL_MASK (ULL(0x7) << CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT)
/*******************************************************************************
* L2 Memory Error Syndrome register specific definitions.

15
include/lib/cpus/aarch32/cortex_a72.h
View File

@ -6,6 +6,7 @@
#ifndef __CORTEX_A72_H__
#define __CORTEX_A72_H__
#include <utils_def.h>
/* Cortex-A72 midr for revision 0 */
#define CORTEX_A72_MIDR 0x410FD080
@ -15,10 +16,10 @@
******************************************************************************/
#define CORTEX_A72_ECTLR p15, 1, c15
#define CORTEX_A72_ECTLR_SMP_BIT (1 << 6)
#define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38)
#define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35)
#define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32)
#define CORTEX_A72_ECTLR_SMP_BIT (ULL(1) << 6)
#define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38)
#define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35)
#define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32)
/*******************************************************************************
* CPU Memory Error Syndrome register specific definitions.
@ -30,9 +31,9 @@
******************************************************************************/
#define CORTEX_A72_ACTLR p15, 0, c15
#define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH (1 << 56)
#define CORTEX_A72_ACTLR_NO_ALLOC_WBWA (1 << 49)
#define CORTEX_A72_ACTLR_DCC_AS_DCCI (1 << 44)
#define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH (ULL(1) << 56)
#define CORTEX_A72_ACTLR_NO_ALLOC_WBWA (ULL(1) << 49)
#define CORTEX_A72_ACTLR_DCC_AS_DCCI (ULL(1) << 44)
/*******************************************************************************
* L2 Control register specific definitions.

1
include/lib/cpus/aarch64/cortex_a57.h
View File

@ -6,6 +6,7 @@
#ifndef __CORTEX_A57_H__
#define __CORTEX_A57_H__
#include <utils_def.h>
/* Cortex-A57 midr for revision 0 */
#define CORTEX_A57_MIDR U(0x410FD070)

15
include/lib/cpus/aarch64/cortex_a72.h
View File

@ -6,6 +6,7 @@
#ifndef __CORTEX_A72_H__
#define __CORTEX_A72_H__
#include <utils_def.h>
/* Cortex-A72 midr for revision 0 */
#define CORTEX_A72_MIDR 0x410FD080
@ -15,10 +16,10 @@
******************************************************************************/
#define CORTEX_A72_ECTLR_EL1 S3_1_C15_C2_1
#define CORTEX_A72_ECTLR_SMP_BIT (1 << 6)
#define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38)
#define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35)
#define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32)
#define CORTEX_A72_ECTLR_SMP_BIT (ULL(1) << 6)
#define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38)
#define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35)
#define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32)
/*******************************************************************************
* CPU Memory Error Syndrome register specific definitions.
@ -30,9 +31,9 @@
******************************************************************************/
#define CORTEX_A72_ACTLR_EL1 S3_1_C15_C2_0
#define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH (1 << 56)
#define CORTEX_A72_ACTLR_NO_ALLOC_WBWA (1 << 49)
#define CORTEX_A72_ACTLR_DCC_AS_DCCI (1 << 44)
#define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH (ULL(1) << 56)
#define CORTEX_A72_ACTLR_NO_ALLOC_WBWA (ULL(1) << 49)
#define CORTEX_A72_ACTLR_DCC_AS_DCCI (ULL(1) << 44)
/*******************************************************************************
* L2 Control register specific definitions.

Write Preview
Loading…
Cancel
Save