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Merge changes from topics "qemu", "qemu_sbsa" into integration 

* changes:
  feat(qemu): add A76/N1 cpu support for virt
  feat(qemu): add "neoverse-n1" cpu support
  feat(qemu): make coherent memory section optional
  refactor(qemu): make use of setup_page_tables()
pull/1995/head
Bipin Ravi 2 years ago
committed by TrustedFirmware Code Review
parent
7419b7a72e 6b66693685
commit
e550fa127f
7 changed files with 160 additions and 95 deletions
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  1. 43
      plat/qemu/common/qemu_bl1_setup.c
  2. 47
      plat/qemu/common/qemu_bl2_setup.c
  3. 38
      plat/qemu/common/qemu_bl31_setup.c
  4. 43
      plat/qemu/common/qemu_common.c
  5. 17
      plat/qemu/common/qemu_private.h
  6. 42
      plat/qemu/qemu/platform.mk
  7. 25
      plat/qemu/qemu_sbsa/platform.mk

43
plat/qemu/common/qemu_bl1_setup.c
View File

@ -14,6 +14,29 @@
#include "qemu_private.h"
#define MAP_BL1_TOTAL MAP_REGION_FLAT( \
bl1_tzram_layout.total_base, \
bl1_tzram_layout.total_size, \
MT_MEMORY | MT_RW | EL3_PAS)
#define MAP_BL1_RO MAP_REGION_FLAT( \
BL_CODE_BASE, \
BL1_CODE_END - BL_CODE_BASE, \
MT_CODE | EL3_PAS), \
MAP_REGION_FLAT( \
BL1_RO_DATA_BASE, \
BL1_RO_DATA_END \
- BL_RO_DATA_BASE, \
MT_RO_DATA | EL3_PAS)
#if USE_COHERENT_MEM
#define MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \
BL_COHERENT_RAM_BASE, \
BL_COHERENT_RAM_END \
- BL_COHERENT_RAM_BASE, \
MT_DEVICE | MT_RW | EL3_PAS)
#endif
/* Data structure which holds the extents of the trusted SRAM for BL1*/
static meminfo_t bl1_tzram_layout;
@ -49,11 +72,21 @@ void bl1_early_platform_setup(void)
void bl1_plat_arch_setup(void)
{
QEMU_CONFIGURE_BL1_MMU(bl1_tzram_layout.total_base,
bl1_tzram_layout.total_size,
BL_CODE_BASE, BL1_CODE_END,
BL1_RO_DATA_BASE, BL1_RO_DATA_END,
BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END);
const mmap_region_t bl_regions[] = {
MAP_BL1_TOTAL,
MAP_BL1_RO,
#if USE_COHERENT_MEM
MAP_BL_COHERENT_RAM,
#endif
{0}
};
setup_page_tables(bl_regions, plat_qemu_get_mmap());
#ifdef __aarch64__
enable_mmu_el3(0);
#else
enable_mmu_svc_mon(0);
#endif
}
void bl1_platform_setup(void)

47
plat/qemu/common/qemu_bl2_setup.c
View File

@ -23,6 +23,28 @@
#include "qemu_private.h"
#define MAP_BL2_TOTAL MAP_REGION_FLAT( \
bl2_tzram_layout.total_base, \
bl2_tzram_layout.total_size, \
MT_MEMORY | MT_RW | MT_SECURE)
#define MAP_BL2_RO MAP_REGION_FLAT( \
BL_CODE_BASE, \
BL_CODE_END - BL_CODE_BASE, \
MT_CODE | MT_SECURE), \
MAP_REGION_FLAT( \
BL_RO_DATA_BASE, \
BL_RO_DATA_END \
- BL_RO_DATA_BASE, \
MT_RO_DATA | MT_SECURE)
#if USE_COHERENT_MEM
#define MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \
BL_COHERENT_RAM_BASE, \
BL_COHERENT_RAM_END \
- BL_COHERENT_RAM_BASE, \
MT_DEVICE | MT_RW | MT_SECURE)
#endif
/* Data structure which holds the extents of the trusted SRAM for BL2 */
static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
@ -83,19 +105,24 @@ void bl2_platform_setup(void)
/* TODO Initialize timer */
}
void bl2_plat_arch_setup(void)
{
const mmap_region_t bl_regions[] = {
MAP_BL2_TOTAL,
MAP_BL2_RO,
#if USE_COHERENT_MEM
MAP_BL_COHERENT_RAM,
#endif
{0}
};
setup_page_tables(bl_regions, plat_qemu_get_mmap());
#ifdef __aarch64__
#define QEMU_CONFIGURE_BL2_MMU(...) qemu_configure_mmu_el1(__VA_ARGS__)
enable_mmu_el1(0);
#else
#define QEMU_CONFIGURE_BL2_MMU(...) qemu_configure_mmu_svc_mon(__VA_ARGS__)
enable_mmu_svc_mon(0);
#endif
void bl2_plat_arch_setup(void)
{
QEMU_CONFIGURE_BL2_MMU(bl2_tzram_layout.total_base,
bl2_tzram_layout.total_size,
BL_CODE_BASE, BL_CODE_END,
BL_RO_DATA_BASE, BL_RO_DATA_END,
BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END);
}
/*******************************************************************************

38
plat/qemu/common/qemu_bl31_setup.c
View File

@ -12,6 +12,28 @@
#include "qemu_private.h"
#define MAP_BL31_TOTAL MAP_REGION_FLAT( \
BL31_BASE, \
BL31_END - BL31_BASE, \
MT_MEMORY | MT_RW | EL3_PAS)
#define MAP_BL31_RO MAP_REGION_FLAT( \
BL_CODE_BASE, \
BL_CODE_END - BL_CODE_BASE, \
MT_CODE | EL3_PAS), \
MAP_REGION_FLAT( \
BL_RO_DATA_BASE, \
BL_RO_DATA_END \
- BL_RO_DATA_BASE, \
MT_RO_DATA | EL3_PAS)
#if USE_COHERENT_MEM
#define MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \
BL_COHERENT_RAM_BASE, \
BL_COHERENT_RAM_END \
- BL_COHERENT_RAM_BASE, \
MT_DEVICE | MT_RW | EL3_PAS)
#endif
/*
* Placeholder variables for copying the arguments that have been passed to
* BL3-1 from BL2.
@ -64,10 +86,18 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
void bl31_plat_arch_setup(void)
{
qemu_configure_mmu_el3(BL31_BASE, (BL31_END - BL31_BASE),
BL_CODE_BASE, BL_CODE_END,
BL_RO_DATA_BASE, BL_RO_DATA_END,
BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END);
const mmap_region_t bl_regions[] = {
MAP_BL31_TOTAL,
MAP_BL31_RO,
#if USE_COHERENT_MEM
MAP_BL_COHERENT_RAM,
#endif
{0}
};
setup_page_tables(bl_regions, plat_qemu_get_mmap());
enable_mmu_el3(0);
}
static void qemu_gpio_init(void)

43
plat/qemu/common/qemu_common.c
View File

@ -122,45 +122,12 @@ static const mmap_region_t plat_qemu_mmap[] = {
#endif
/*******************************************************************************
* Macro generating the code for the function setting up the pagetables as per
* the platform memory map & initialize the mmu, for the given exception level
* Returns QEMU platform specific memory map regions.
******************************************************************************/
#define DEFINE_CONFIGURE_MMU_EL(_el) \
void qemu_configure_mmu_##_el(unsigned long total_base, \
unsigned long total_size, \
unsigned long code_start, \
unsigned long code_limit, \
unsigned long ro_start, \
unsigned long ro_limit, \
unsigned long coh_start, \
unsigned long coh_limit) \
{ \
mmap_add_region(total_base, total_base, \
total_size, \
MT_MEMORY | MT_RW | MT_SECURE); \
mmap_add_region(code_start, code_start, \
code_limit - code_start, \
MT_CODE | MT_SECURE); \
mmap_add_region(ro_start, ro_start, \
ro_limit - ro_start, \
MT_RO_DATA | MT_SECURE); \
mmap_add_region(coh_start, coh_start, \
coh_limit - coh_start, \
MT_DEVICE | MT_RW | MT_SECURE); \
mmap_add(plat_qemu_mmap); \
init_xlat_tables(); \
\
enable_mmu_##_el(0); \
}
/* Define EL1 and EL3 variants of the function initialising the MMU */
#ifdef __aarch64__
DEFINE_CONFIGURE_MMU_EL(el1)
DEFINE_CONFIGURE_MMU_EL(el3)
#else
DEFINE_CONFIGURE_MMU_EL(svc_mon)
#endif
const mmap_region_t *plat_qemu_get_mmap(void)
{
return plat_qemu_mmap;
}
#if MEASURED_BOOT || TRUSTED_BOARD_BOOT
int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)

17
plat/qemu/common/qemu_private.h
View File

@ -9,26 +9,13 @@
#include <stdint.h>
void qemu_configure_mmu_svc_mon(unsigned long total_base,
unsigned long total_size,
unsigned long code_start, unsigned long code_limit,
unsigned long ro_start, unsigned long ro_limit,
unsigned long coh_start, unsigned long coh_limit);
void qemu_configure_mmu_el1(unsigned long total_base, unsigned long total_size,
unsigned long code_start, unsigned long code_limit,
unsigned long ro_start, unsigned long ro_limit,
unsigned long coh_start, unsigned long coh_limit);
void qemu_configure_mmu_el3(unsigned long total_base, unsigned long total_size,
unsigned long code_start, unsigned long code_limit,
unsigned long ro_start, unsigned long ro_limit,
unsigned long coh_start, unsigned long coh_limit);
#include <lib/xlat_tables/xlat_tables_compat.h>
void plat_qemu_io_setup(void);
int qemu_io_register_sp_pkg(const char *name, const char *uuid,
uintptr_t load_addr);
unsigned int plat_qemu_calc_core_pos(u_register_t mpidr);
const mmap_region_t *plat_qemu_get_mmap(void);
void qemu_console_init(void);

42
plat/qemu/qemu/platform.mk
View File

@ -18,6 +18,17 @@ $(eval $(call add_define,ARMV7_SUPPORTS_GENERIC_TIMER))
$(eval $(call add_define,ARMV7_SUPPORTS_VFP))
# Qemu expects a BL32 boot stage.
NEED_BL32 := yes
else
CTX_INCLUDE_AARCH32_REGS := 0
ifeq (${CTX_INCLUDE_AARCH32_REGS}, 1)
$(error "This is an AArch64-only port; CTX_INCLUDE_AARCH32_REGS must be disabled")
endif
# Treating this as a memory-constrained port for now
USE_COHERENT_MEM := 0
# This can be overridden depending on CPU(s) used in the QEMU image
HW_ASSISTED_COHERENCY := 1
endif # ARMv7
ifeq (${SPD},opteed)
@ -46,6 +57,17 @@ PLAT_INCLUDES := -Iinclude/plat/arm/common/ \
ifeq (${ARM_ARCH_MAJOR},8)
PLAT_INCLUDES += -Iinclude/plat/arm/common/${ARCH}
QEMU_CPU_LIBS := lib/cpus/aarch64/aem_generic.S \
lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/cortex_a57.S \
lib/cpus/aarch64/cortex_a72.S \
lib/cpus/aarch64/cortex_a76.S \
lib/cpus/aarch64/neoverse_n_common.S \
lib/cpus/aarch64/neoverse_n1.S \
lib/cpus/aarch64/qemu_max.S
else
QEMU_CPU_LIBS := lib/cpus/${ARCH}/cortex_a15.S
endif
PLAT_BL_COMMON_SOURCES := ${PLAT_QEMU_COMMON_PATH}/qemu_common.c \
@ -135,18 +157,8 @@ BL1_SOURCES += drivers/io/io_semihosting.c \
lib/semihosting/${ARCH}/semihosting_call.S \
${PLAT_QEMU_COMMON_PATH}/qemu_io_storage.c \
${PLAT_QEMU_COMMON_PATH}/${ARCH}/plat_helpers.S \
${PLAT_QEMU_COMMON_PATH}/qemu_bl1_setup.c
ifeq (${ARM_ARCH_MAJOR},8)
BL1_SOURCES += lib/cpus/aarch64/aem_generic.S \
lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/cortex_a57.S \
lib/cpus/aarch64/cortex_a72.S \
lib/cpus/aarch64/qemu_max.S \
else
BL1_SOURCES += lib/cpus/${ARCH}/cortex_a15.S
endif
${PLAT_QEMU_COMMON_PATH}/qemu_bl1_setup.c \
${QEMU_CPU_LIBS}
BL2_SOURCES += drivers/io/io_semihosting.c \
drivers/io/io_storage.c \
@ -195,11 +207,7 @@ $(error "Incorrect GIC driver chosen for QEMU platform")
endif
ifeq (${ARM_ARCH_MAJOR},8)
BL31_SOURCES += lib/cpus/aarch64/aem_generic.S \
lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/cortex_a57.S \
lib/cpus/aarch64/cortex_a72.S \
lib/cpus/aarch64/qemu_max.S \
BL31_SOURCES += ${QEMU_CPU_LIBS} \
lib/semihosting/semihosting.c \
lib/semihosting/${ARCH}/semihosting_call.S \
plat/common/plat_psci_common.c \

25
plat/qemu/qemu_sbsa/platform.mk
View File

@ -19,6 +19,11 @@ endif
# Enable new version of image loading on QEMU platforms
LOAD_IMAGE_V2 := 1
CTX_INCLUDE_AARCH32_REGS := 0
ifeq (${CTX_INCLUDE_AARCH32_REGS}, 1)
$(error "This is an AArch64-only port; CTX_INCLUDE_AARCH32_REGS must be disabled")
endif
ifeq ($(NEED_BL32),yes)
$(eval $(call add_define,QEMU_LOAD_BL32))
endif
@ -36,6 +41,18 @@ PLAT_BL_COMMON_SOURCES := ${PLAT_QEMU_COMMON_PATH}/qemu_common.c \
${PLAT_QEMU_COMMON_PATH}/qemu_console.c \
drivers/arm/pl011/${ARCH}/pl011_console.S
# Treating this as a memory-constrained port for now
USE_COHERENT_MEM := 0
# This can be overridden depending on CPU(s) used in the QEMU image
HW_ASSISTED_COHERENCY := 1
QEMU_CPU_LIBS := lib/cpus/aarch64/cortex_a57.S \
lib/cpus/aarch64/cortex_a72.S \
lib/cpus/aarch64/neoverse_n_common.S \
lib/cpus/aarch64/neoverse_n1.S \
lib/cpus/aarch64/qemu_max.S
include lib/xlat_tables_v2/xlat_tables.mk
PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS}
@ -49,9 +66,7 @@ BL1_SOURCES += drivers/io/io_semihosting.c \
${PLAT_QEMU_COMMON_PATH}/${ARCH}/plat_helpers.S \
${PLAT_QEMU_COMMON_PATH}/qemu_bl1_setup.c
BL1_SOURCES += lib/cpus/aarch64/cortex_a57.S \
lib/cpus/aarch64/cortex_a72.S \
lib/cpus/aarch64/qemu_max.S \
BL1_SOURCES += ${QEMU_CPU_LIBS}
BL2_SOURCES += drivers/io/io_semihosting.c \
drivers/io/io_storage.c \
@ -77,9 +92,7 @@ QEMU_GIC_SOURCES := ${GICV3_SOURCES} \
plat/common/plat_gicv3.c \
${PLAT_QEMU_COMMON_PATH}/qemu_gicv3.c
BL31_SOURCES += lib/cpus/aarch64/cortex_a57.S \
lib/cpus/aarch64/cortex_a72.S \
lib/cpus/aarch64/qemu_max.S \
BL31_SOURCES += ${QEMU_CPU_LIBS} \
lib/semihosting/semihosting.c \
lib/semihosting/${ARCH}/semihosting_call.S \
plat/common/plat_psci_common.c \

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