plat/arm/board/arm_fpga: Enable port for alternative cluster configurations

This change is part of the goal of enabling the port to be compatible
with multiple FPGA images.

The BL31 port that is uploaded as a payload to the FPGA with an image
should cater for a wide variety of system configurations. This patch
makes the necessary changes to enable it to function with images whose
cluster configurations may be larger (either by utilizing more
clusters, more CPUs per cluster, more threads in each CPU, or a
combination) than the initial image being used for testing.

As part of this, the hard-coded values that configure the size of the
array describing the topology of the power domain tree are increased
to max. 8 clusters, max. 8 cores per cluster & max 4 threads per core.
This ensures the port works with cluster configurations up to these
sizes. When there are too many entries for the number of available PEs,
e.g. if there is a variable number of CPUs between clusters, then there
will be empty entries in the array. This is permitted and the PSCI
library will still function as expected. While this increases its size,
this shouldn't be an issue in the context of the size of BL31, and is
worth the trade-off for the extra compatibility.

Signed-off-by: Oliver Swede <oli.swede@arm.com>
Change-Id: I7d4ae1e20b2e99fdbac428d122a2cf9445394363

plat/arm/board/arm_fpga/fpga_def.h

@@ -10,12 +10,17 @@
 #define FPGA_DEF_H
 
 /*
- * The initial FPGA image configures a system with 2 clusters, 1 core in each,
- * and multi-threading is unimplemented.
+ * These are set to large values to account for images describing systems with
+ * larger cluster configurations.
+ *
+ * For cases where the number of clusters, cores or threads is smaller than a
+ * maximum value below, this does not affect the PSCI functionality as any PEs
+ * that are present will still be indexed appropriately regardless of any empty
+ * entries in the array used to represent the topology.
  */
 #define FPGA_MAX_CLUSTER_COUNT			2
-#define FPGA_MAX_CPUS_PER_CLUSTER		1
-#define FPGA_MAX_PE_PER_CPU			1
+#define FPGA_MAX_CPUS_PER_CLUSTER		8
+#define FPGA_MAX_PE_PER_CPU			4
 
 #define FPGA_PRIMARY_CPU			0x0
 

plat/arm/board/arm_fpga/platform.mk

@@ -9,6 +9,10 @@ ifeq (${RESET_TO_BL31}, 0)
 $(error "This is a BL31-only port; RESET_TO_BL31 must be enabled")
 endif
 
+ifeq (${ENABLE_PIE}, 1)
+override SEPARATE_CODE_AND_RODATA := 1
+endif
+
 CTX_INCLUDE_AARCH32_REGS := 0
 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 1)
 $(error "This is an AArch64-only port; CTX_INCLUDE_AARCH32_REGS must be disabled")