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Merge changes from topic "gr/cpu_rename" into integration 

* changes:
  chore: rename hayes to a520
  chore: rename hunter to a720
  chore: rename hunter_elp to cortex-x4
pull/1999/head
Madhukar Pappireddy 1 year ago
committed by TrustedFirmware Code Review
parent
0bc2f3d2bb dea3d71e9a
commit
e87102f32b
11 changed files with 142 additions and 143 deletions
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  1. 7
      docs/plat/arm/tc/index.rst
  2. 2
      docs/security_advisories/security-advisory-tfv-9.rst
  3. 16
      include/lib/cpus/aarch64/cortex_a520.h
  4. 20
      include/lib/cpus/aarch64/cortex_a720.h
  5. 26
      include/lib/cpus/aarch64/cortex_hunter_elp_arm.h
  6. 26
      include/lib/cpus/aarch64/cortex_x4.h
  7. 48
      lib/cpus/aarch64/cortex_a520.S
  8. 56
      lib/cpus/aarch64/cortex_a720.S
  9. 56
      lib/cpus/aarch64/cortex_x4.S
  10. 22
      plat/arm/board/arm_fpga/platform.mk
  11. 6
      plat/arm/board/tc/platform.mk

7
docs/plat/arm/tc/index.rst
View File

@ -18,9 +18,8 @@ Currently, the main difference between TC0 (TARGET_PLATFORM=0), TC1
is the CPUs supported as below:
- TC0 has support for Cortex A510, Cortex A710 and Cortex X2. (Note TC0 is now deprecated)
- TC1 has support for Cortex A510, Cortex Makalu and Cortex X3.
- TC2 has support for Hayes and Hunter Arm CPUs.
- TC1 has support for Cortex A510, Cortex A715 and Cortex X3.
- TC2 has support for Cortex A520, Cortex A720 and Cortex x4.
Boot Sequence
-------------
@ -58,6 +57,6 @@ Build Procedure (TF-A only)
--------------
*Copyright (c) 2020-2022, Arm Limited. All rights reserved.*
*Copyright (c) 2020-2023, Arm Limited. All rights reserved.*
.. _Arm Toolchain: https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/downloads

2
docs/security_advisories/security-advisory-tfv-9.rst
View File

@ -77,7 +77,7 @@ revisions of Cortex-A73 and Cortex-A75 that implements FEAT_CSV2).
+----------------------+
| Cortex-A715 |
+----------------------+
| Cortex-Hunter |
| Cortex-A720 |
+----------------------+
| Neoverse-N1 |
+----------------------+

16
include/lib/cpus/aarch64/cortex_hayes.h → include/lib/cpus/aarch64/cortex_a520.h
View File

@ -1,23 +1,23 @@
/*
* Copyright (c) 2021, Arm Limited. All rights reserved.
* Copyright (c) 2021-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef CORTEX_HAYES_H
#define CORTEX_HAYES_H
#ifndef CORTEX_A520_H
#define CORTEX_A520_H
#define CORTEX_HAYES_MIDR U(0x410FD800)
#define CORTEX_A520_MIDR U(0x410FD800)
/*******************************************************************************
* CPU Extended Control register specific definitions
******************************************************************************/
#define CORTEX_HAYES_CPUECTLR_EL1 S3_0_C15_C1_4
#define CORTEX_A520_CPUECTLR_EL1 S3_0_C15_C1_4
/*******************************************************************************
* CPU Power Control register specific definitions
******************************************************************************/
#define CORTEX_HAYES_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define CORTEX_HAYES_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
#define CORTEX_A520_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define CORTEX_A520_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
#endif /* CORTEX_HAYES_H */
#endif /* CORTEX_A520_H */

20
include/lib/cpus/aarch64/cortex_hunter.h → include/lib/cpus/aarch64/cortex_a720.h
View File

@ -1,26 +1,26 @@
/*
* Copyright (c) 2021-2022, Arm Limited. All rights reserved.
* Copyright (c) 2021-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef CORTEX_HUNTER_H
#define CORTEX_HUNTER_H
#ifndef CORTEX_A720_H
#define CORTEX_A720_H
#define CORTEX_HUNTER_MIDR U(0x410FD810)
#define CORTEX_A720_MIDR U(0x410FD810)
/* Cortex Hunter loop count for CVE-2022-23960 mitigation */
#define CORTEX_HUNTER_BHB_LOOP_COUNT U(132)
/* Cortex A720 loop count for CVE-2022-23960 mitigation */
#define CORTEX_A720_BHB_LOOP_COUNT U(132)
/*******************************************************************************
* CPU Extended Control register specific definitions
******************************************************************************/
#define CORTEX_HUNTER_CPUECTLR_EL1 S3_0_C15_C1_4
#define CORTEX_A720_CPUECTLR_EL1 S3_0_C15_C1_4
/*******************************************************************************
* CPU Power Control register specific definitions
******************************************************************************/
#define CORTEX_HUNTER_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define CORTEX_HUNTER_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
#define CORTEX_A720_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define CORTEX_A720_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
#endif /* CORTEX_HUNTER_H */
#endif /* CORTEX_A720_H */

26
include/lib/cpus/aarch64/cortex_hunter_elp_arm.h
View File

@ -1,26 +0,0 @@
/*
* Copyright (c) 2022, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef CORTEX_HUNTER_ELP_ARM_H
#define CORTEX_HUNTER_ELP_ARM_H
#define CORTEX_HUNTER_ELP_ARM_MIDR U(0x410FD821)
/* Cortex Hunter ELP loop count for CVE-2022-23960 mitigation */
#define CORTEX_HUNTER_ELP_ARM_BHB_LOOP_COUNT U(132)
/*******************************************************************************
* CPU Extended Control register specific definitions
******************************************************************************/
#define CORTEX_HUNTER_ELP_ARM_CPUECTLR_EL1 S3_0_C15_C1_4
/*******************************************************************************
* CPU Power Control register specific definitions
******************************************************************************/
#define CORTEX_HUNTER_ELP_ARM_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define CORTEX_HUNTER_ELP_ARM_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
#endif /* CORTEX_HUNTER_ELP_ARM_H */

26
include/lib/cpus/aarch64/cortex_x4.h
View File

@ -0,0 +1,26 @@
/*
* Copyright (c) 2022-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef CORTEX_X4_H
#define CORTEX_X4_H
#define CORTEX_X4_MIDR U(0x410FD821)
/* Cortex X4 loop count for CVE-2022-23960 mitigation */
#define CORTEX_X4_BHB_LOOP_COUNT U(132)
/*******************************************************************************
* CPU Extended Control register specific definitions
******************************************************************************/
#define CORTEX_X4_CPUECTLR_EL1 S3_0_C15_C1_4
/*******************************************************************************
* CPU Power Control register specific definitions
******************************************************************************/
#define CORTEX_X4_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define CORTEX_X4_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
#endif /* CORTEX_X4_H */

48
lib/cpus/aarch64/cortex_hayes.S → lib/cpus/aarch64/cortex_a520.S
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2021, Arm Limited. All rights reserved.
* Copyright (c) 2021-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -7,54 +7,54 @@
#include <arch.h>
#include <asm_macros.S>
#include <common/bl_common.h>
#include <cortex_hayes.h>
#include <cortex_a520.h>
#include <cpu_macros.S>
#include <plat_macros.S>
/* Hardware handled coherency */
#if HW_ASSISTED_COHERENCY == 0
#error "Cortex Hayes must be compiled with HW_ASSISTED_COHERENCY enabled"
#error "Cortex A520 must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif
/* 64-bit only core */
#if CTX_INCLUDE_AARCH32_REGS == 1
#error "Cortex Hayes supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#error "Cortex A520 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
* ----------------------------------------------------
*/
func cortex_hayes_core_pwr_dwn
func cortex_a520_core_pwr_dwn
/* ---------------------------------------------------
* Enable CPU power down bit in power control register
* ---------------------------------------------------
*/
mrs x0, CORTEX_HAYES_CPUPWRCTLR_EL1
orr x0, x0, #CORTEX_HAYES_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
msr CORTEX_HAYES_CPUPWRCTLR_EL1, x0
mrs x0, CORTEX_A520_CPUPWRCTLR_EL1
orr x0, x0, #CORTEX_A520_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
msr CORTEX_A520_CPUPWRCTLR_EL1, x0
isb
ret
endfunc cortex_hayes_core_pwr_dwn
endfunc cortex_a520_core_pwr_dwn
/*
* Errata printing function for Cortex Hayes. Must follow AAPCS.
* Errata printing function for Cortex A520. Must follow AAPCS.
*/
#if REPORT_ERRATA
func cortex_hayes_errata_report
func cortex_a520_errata_report
ret
endfunc cortex_hayes_errata_report
endfunc cortex_a520_errata_report
#endif
func cortex_hayes_reset_func
func cortex_a520_reset_func
/* Disable speculative loads */
msr SSBS, xzr
isb
ret
endfunc cortex_hayes_reset_func
endfunc cortex_a520_reset_func
/* ---------------------------------------------
* This function provides Cortex Hayes specific
* This function provides Cortex A520 specific
* register information for crash reporting.
* It needs to return with x6 pointing to
* a list of register names in ascii and
@ -62,16 +62,16 @@ endfunc cortex_hayes_reset_func
* reported.
* ---------------------------------------------
*/
.section .rodata.cortex_hayes_regs, "aS"
cortex_hayes_regs: /* The ascii list of register names to be reported */
.section .rodata.cortex_a520_regs, "aS"
cortex_a520_regs: /* The ascii list of register names to be reported */
.asciz "cpuectlr_el1", ""
func cortex_hayes_cpu_reg_dump
adr x6, cortex_hayes_regs
mrs x8, CORTEX_HAYES_CPUECTLR_EL1
func cortex_a520_cpu_reg_dump
adr x6, cortex_a520_regs
mrs x8, CORTEX_A520_CPUECTLR_EL1
ret
endfunc cortex_hayes_cpu_reg_dump
endfunc cortex_a520_cpu_reg_dump
declare_cpu_ops cortex_hayes, CORTEX_HAYES_MIDR, \
cortex_hayes_reset_func, \
cortex_hayes_core_pwr_dwn
declare_cpu_ops cortex_a520, CORTEX_A520_MIDR, \
cortex_a520_reset_func, \
cortex_a520_core_pwr_dwn

56
lib/cpus/aarch64/cortex_hunter.S → lib/cpus/aarch64/cortex_a720.S
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2021-2022, Arm Limited. All rights reserved.
* Copyright (c) 2021-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -7,23 +7,23 @@
#include <arch.h>
#include <asm_macros.S>
#include <common/bl_common.h>
#include <cortex_hunter.h>
#include <cortex_a720.h>
#include <cpu_macros.S>
#include <plat_macros.S>
#include "wa_cve_2022_23960_bhb_vector.S"
/* Hardware handled coherency */
#if HW_ASSISTED_COHERENCY == 0
#error "Cortex Hunter must be compiled with HW_ASSISTED_COHERENCY enabled"
#error "Cortex A720 must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif
/* 64-bit only core */
#if CTX_INCLUDE_AARCH32_REGS == 1
#error "Cortex Hunter supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#error "Cortex A720 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
#if WORKAROUND_CVE_2022_23960
wa_cve_2022_23960_bhb_vector_table CORTEX_HUNTER_BHB_LOOP_COUNT, cortex_hunter
wa_cve_2022_23960_bhb_vector_table CORTEX_A720_BHB_LOOP_COUNT, cortex_a720
#endif /* WORKAROUND_CVE_2022_23960 */
func check_errata_cve_2022_23960
@ -35,44 +35,44 @@ func check_errata_cve_2022_23960
ret
endfunc check_errata_cve_2022_23960
func cortex_hunter_reset_func
func cortex_a720_reset_func
/* Disable speculative loads */
msr SSBS, xzr
#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
/*
* The Cortex Hunter generic vectors are overridden to apply errata
* The Cortex A720 generic vectors are overridden to apply errata
* mitigation on exception entry from lower ELs.
*/
adr x0, wa_cve_vbar_cortex_hunter
adr x0, wa_cve_vbar_cortex_a720
msr vbar_el3, x0
#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
isb
ret
endfunc cortex_hunter_reset_func
endfunc cortex_a720_reset_func
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
* ----------------------------------------------------
*/
func cortex_hunter_core_pwr_dwn
func cortex_a720_core_pwr_dwn
/* ---------------------------------------------------
* Enable CPU power down bit in power control register
* ---------------------------------------------------
*/
mrs x0, CORTEX_HUNTER_CPUPWRCTLR_EL1
orr x0, x0, #CORTEX_HUNTER_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
msr CORTEX_HUNTER_CPUPWRCTLR_EL1, x0
mrs x0, CORTEX_A720_CPUPWRCTLR_EL1
orr x0, x0, #CORTEX_A720_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
msr CORTEX_A720_CPUPWRCTLR_EL1, x0
isb
ret
endfunc cortex_hunter_core_pwr_dwn
endfunc cortex_a720_core_pwr_dwn
#if REPORT_ERRATA
/*
* Errata printing function for Cortex Hunter. Must follow AAPCS.
* Errata printing function for Cortex A720. Must follow AAPCS.
*/
func cortex_hunter_errata_report
func cortex_a720_errata_report
stp x8, x30, [sp, #-16]!
bl cpu_get_rev_var
@ -82,15 +82,15 @@ func cortex_hunter_errata_report
* Report all errata. The revision-variant information is passed to
* checking functions of each errata.
*/
report_errata WORKAROUND_CVE_2022_23960, cortex_hunter, cve_2022_23960
report_errata WORKAROUND_CVE_2022_23960, cortex_a720, cve_2022_23960
ldp x8, x30, [sp], #16
ret
endfunc cortex_hunter_errata_report
endfunc cortex_a720_errata_report
#endif
/* ---------------------------------------------
* This function provides Cortex Hunter-specific
* This function provides Cortex A720-specific
* register information for crash reporting.
* It needs to return with x6 pointing to
* a list of register names in ascii and
@ -98,16 +98,16 @@ endfunc cortex_hunter_errata_report
* reported.
* ---------------------------------------------
*/
.section .rodata.cortex_hunter_regs, "aS"
cortex_hunter_regs: /* The ascii list of register names to be reported */
.section .rodata.cortex_a720_regs, "aS"
cortex_a720_regs: /* The ascii list of register names to be reported */
.asciz "cpuectlr_el1", ""
func cortex_hunter_cpu_reg_dump
adr x6, cortex_hunter_regs
mrs x8, CORTEX_HUNTER_CPUECTLR_EL1
func cortex_a720_cpu_reg_dump
adr x6, cortex_a720_regs
mrs x8, CORTEX_A720_CPUECTLR_EL1
ret
endfunc cortex_hunter_cpu_reg_dump
endfunc cortex_a720_cpu_reg_dump
declare_cpu_ops cortex_hunter, CORTEX_HUNTER_MIDR, \
cortex_hunter_reset_func, \
cortex_hunter_core_pwr_dwn
declare_cpu_ops cortex_a720, CORTEX_A720_MIDR, \
cortex_a720_reset_func, \
cortex_a720_core_pwr_dwn

56
lib/cpus/aarch64/cortex_hunter_elp_arm.S → lib/cpus/aarch64/cortex_x4.S
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2022, Arm Limited. All rights reserved.
* Copyright (c) 2022-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -7,23 +7,23 @@
#include <arch.h>
#include <asm_macros.S>
#include <common/bl_common.h>
#include <cortex_hunter_elp_arm.h>
#include <cortex_x4.h>
#include <cpu_macros.S>
#include <plat_macros.S>
#include "wa_cve_2022_23960_bhb_vector.S"
/* Hardware handled coherency */
#if HW_ASSISTED_COHERENCY == 0
#error "Cortex Hunter ELP must be compiled with HW_ASSISTED_COHERENCY enabled"
#error "Cortex X4 must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif
/* 64-bit only core */
#if CTX_INCLUDE_AARCH32_REGS == 1
#error "Cortex Hunter ELP supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#error "Cortex X4 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
#if WORKAROUND_CVE_2022_23960
wa_cve_2022_23960_bhb_vector_table CORTEX_HUNTER_ELP_ARM_BHB_LOOP_COUNT, cortex_hunter_elp_arm
wa_cve_2022_23960_bhb_vector_table CORTEX_X4_BHB_LOOP_COUNT, cortex_x4
#endif /* WORKAROUND_CVE_2022_23960 */
func check_errata_cve_2022_23960
@ -35,44 +35,44 @@ func check_errata_cve_2022_23960
ret
endfunc check_errata_cve_2022_23960
func cortex_hunter_elp_arm_reset_func
func cortex_x4_reset_func
/* Disable speculative loads */
msr SSBS, xzr
#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
/*
* The Cortex Hunter ELP generic vectors are overridden to apply errata
* The Cortex X4 generic vectors are overridden to apply errata
* mitigation on exception entry from lower ELs.
*/
adr x0, wa_cve_vbar_cortex_hunter_elp_arm
adr x0, wa_cve_vbar_cortex_x4
msr vbar_el3, x0
#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
isb
ret
endfunc cortex_hunter_elp_arm_reset_func
endfunc cortex_x4_reset_func
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
* ----------------------------------------------------
*/
func cortex_hunter_elp_arm_core_pwr_dwn
func cortex_x4_core_pwr_dwn
/* ---------------------------------------------------
* Enable CPU power down bit in power control register
* ---------------------------------------------------
*/
mrs x0, CORTEX_HUNTER_ELP_ARM_CPUPWRCTLR_EL1
orr x0, x0, #CORTEX_HUNTER_ELP_ARM_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
msr CORTEX_HUNTER_ELP_ARM_CPUPWRCTLR_EL1, x0
mrs x0, CORTEX_X4_CPUPWRCTLR_EL1
orr x0, x0, #CORTEX_X4_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
msr CORTEX_X4_CPUPWRCTLR_EL1, x0
isb
ret
endfunc cortex_hunter_elp_arm_core_pwr_dwn
endfunc cortex_x4_core_pwr_dwn
#if REPORT_ERRATA
/*
* Errata printing function for Cortex Hunter ELP. Must follow AAPCS.
* Errata printing function for Cortex X4. Must follow AAPCS.
*/
func cortex_hunter_elp_arm_errata_report
func cortex_x4_errata_report
stp x8, x30, [sp, #-16]!
bl cpu_get_rev_var
@ -82,15 +82,15 @@ func cortex_hunter_elp_arm_errata_report
* Report all errata. The revision-variant information is passed to
* checking functions of each errata.
*/
report_errata WORKAROUND_CVE_2022_23960, cortex_hunter_elp_arm, cve_2022_23960
report_errata WORKAROUND_CVE_2022_23960, cortex_x4, cve_2022_23960
ldp x8, x30, [sp], #16
ret
endfunc cortex_hunter_elp_arm_errata_report
endfunc cortex_x4_errata_report
#endif
/* ---------------------------------------------
* This function provides Cortex Hunter ELP-specific
* This function provides Cortex X4-specific
* register information for crash reporting.
* It needs to return with x6 pointing to
* a list of register names in ascii and
@ -98,16 +98,16 @@ endfunc cortex_hunter_elp_arm_errata_report
* reported.
* ---------------------------------------------
*/
.section .rodata.cortex_hunter_elp_arm_regs, "aS"
cortex_hunter_elp_arm_regs: /* The ascii list of register names to be reported */
.section .rodata.cortex_x4_regs, "aS"
cortex_x4_regs: /* The ascii list of register names to be reported */
.asciz "cpuectlr_el1", ""
func cortex_hunter_elp_arm_cpu_reg_dump
adr x6, cortex_hunter_elp_arm_regs
mrs x8, CORTEX_HUNTER_ELP_ARM_CPUECTLR_EL1
func cortex_x4_cpu_reg_dump
adr x6, cortex_x4_regs
mrs x8, CORTEX_X4_CPUECTLR_EL1
ret
endfunc cortex_hunter_elp_arm_cpu_reg_dump
endfunc cortex_x4_cpu_reg_dump
declare_cpu_ops cortex_hunter_elp_arm, CORTEX_HUNTER_ELP_ARM_MIDR, \
cortex_hunter_elp_arm_reset_func, \
cortex_hunter_elp_arm_core_pwr_dwn
declare_cpu_ops cortex_x4, CORTEX_X4_MIDR, \
cortex_x4_reset_func, \
cortex_x4_core_pwr_dwn

22
plat/arm/board/arm_fpga/platform.mk
View File

@ -58,18 +58,18 @@ ifeq (${HW_ASSISTED_COHERENCY}, 0)
lib/cpus/aarch64/cortex_a73.S
else
# AArch64-only cores
FPGA_CPU_LIBS +=lib/cpus/aarch64/cortex_a510.S \
lib/cpus/aarch64/cortex_a710.S \
lib/cpus/aarch64/cortex_a715.S \
lib/cpus/aarch64/cortex_x3.S \
FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a510.S \
lib/cpus/aarch64/cortex_a520.S \
lib/cpus/aarch64/cortex_a710.S \
lib/cpus/aarch64/cortex_a715.S \
lib/cpus/aarch64/cortex_a720.S \
lib/cpus/aarch64/cortex_x3.S \
lib/cpus/aarch64/cortex_x4.S \
lib/cpus/aarch64/neoverse_n_common.S \
lib/cpus/aarch64/neoverse_n1.S \
lib/cpus/aarch64/neoverse_n2.S \
lib/cpus/aarch64/neoverse_v1.S \
lib/cpus/aarch64/cortex_hayes.S \
lib/cpus/aarch64/cortex_hunter.S \
lib/cpus/aarch64/cortex_hunter_elp_arm.S \
lib/cpus/aarch64/cortex_chaberton.S \
lib/cpus/aarch64/neoverse_n1.S \
lib/cpus/aarch64/neoverse_n2.S \
lib/cpus/aarch64/neoverse_v1.S \
lib/cpus/aarch64/cortex_chaberton.S \
lib/cpus/aarch64/cortex_blackhawk.S
# AArch64/AArch32 cores

6
plat/arm/board/tc/platform.mk
View File

@ -78,9 +78,9 @@ endif
# CPU libraries for TARGET_PLATFORM=2
ifeq (${TARGET_PLATFORM}, 2)
TC_CPU_SOURCES += lib/cpus/aarch64/cortex_hayes.S \
lib/cpus/aarch64/cortex_hunter.S \
lib/cpus/aarch64/cortex_hunter_elp_arm.S
TC_CPU_SOURCES += lib/cpus/aarch64/cortex_a520.S \
lib/cpus/aarch64/cortex_a720.S \
lib/cpus/aarch64/cortex_x4.S
endif
INTERCONNECT_SOURCES := ${TC_BASE}/tc_interconnect.c

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