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Merge changes from topic "st-gpio-update" into integration 

* changes:
  feat(st-gpio): do not apply secure config in BL2
  feat(st): get pin_count from the gpio-ranges property
  feat(st-gpio): allow to set a gpio in output mode
  refactor(st-gpio): code improvements
pull/1983/merge
Madhukar Pappireddy 3 years ago
committed by TrustedFirmware Code Review
parent
20eb9d5bba fc0aa10a2c
commit
ed2d29aef4
3 changed files with 104 additions and 56 deletions
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  1. 104
      drivers/st/gpio/stm32_gpio.c
  2. 35
      include/drivers/st/stm32_gpio.h
  3. 21
      plat/st/common/stm32mp_dt.c

104
drivers/st/gpio/stm32_gpio.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2021, STMicroelectronics - All Rights Reserved
* Copyright (c) 2016-2022, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -8,10 +8,6 @@
#include <errno.h>
#include <stdbool.h>
#include <libfdt.h>
#include <platform_def.h>
#include <common/bl_common.h>
#include <common/debug.h>
#include <drivers/clk.h>
@ -19,6 +15,9 @@
#include <drivers/st/stm32mp_clkfunc.h>
#include <lib/mmio.h>
#include <lib/utils_def.h>
#include <libfdt.h>
#include <platform_def.h>
#define DT_GPIO_BANK_SHIFT 12
#define DT_GPIO_BANK_MASK GENMASK(16, 12)
@ -26,6 +25,10 @@
#define DT_GPIO_PIN_MASK GENMASK(11, 8)
#define DT_GPIO_MODE_MASK GENMASK(7, 0)
static void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t type,
uint32_t speed, uint32_t pull, uint32_t od,
uint32_t alternate, uint8_t status);
/*******************************************************************************
* This function gets GPIO bank node in DT.
* Returns node offset if status is okay in DT, else return 0
@ -100,6 +103,8 @@ static int dt_set_gpio_config(void *fdt, int node, uint8_t status)
uint32_t pin;
uint32_t mode;
uint32_t alternate = GPIO_ALTERNATE_(0);
uint32_t type;
uint32_t od = GPIO_OD_OUTPUT_LOW;
int bank_node;
int clk;
@ -129,7 +134,23 @@ static int dt_set_gpio_config(void *fdt, int node, uint8_t status)
}
if (fdt_getprop(fdt, node, "drive-open-drain", NULL) != NULL) {
mode |= GPIO_OPEN_DRAIN;
type = GPIO_TYPE_OPEN_DRAIN;
} else {
type = GPIO_TYPE_PUSH_PULL;
}
if (fdt_getprop(fdt, node, "output-high", NULL) != NULL) {
if (mode == GPIO_MODE_INPUT) {
mode = GPIO_MODE_OUTPUT;
od = GPIO_OD_OUTPUT_HIGH;
}
}
if (fdt_getprop(fdt, node, "output-low", NULL) != NULL) {
if (mode == GPIO_MODE_INPUT) {
mode = GPIO_MODE_OUTPUT;
od = GPIO_OD_OUTPUT_LOW;
}
}
bank_node = ckeck_gpio_bank(fdt, bank, pinctrl_node);
@ -146,7 +167,7 @@ static int dt_set_gpio_config(void *fdt, int node, uint8_t status)
/* Platform knows the clock: assert it is okay */
assert((unsigned long)clk == stm32_get_gpio_bank_clock(bank));
set_gpio(bank, pin, mode, speed, pull, alternate, status);
set_gpio(bank, pin, mode, type, speed, pull, od, alternate, status);
}
return 0;
@ -160,7 +181,7 @@ static int dt_set_gpio_config(void *fdt, int node, uint8_t status)
int dt_set_pinctrl_config(int node)
{
const fdt32_t *cuint;
int lenp = 0;
int lenp;
uint32_t i;
uint8_t status;
void *fdt;
@ -201,8 +222,9 @@ int dt_set_pinctrl_config(int node)
return 0;
}
void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t speed,
uint32_t pull, uint32_t alternate, uint8_t status)
static void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t type,
uint32_t speed, uint32_t pull, uint32_t od,
uint32_t alternate, uint8_t status)
{
uintptr_t base = stm32_get_gpio_bank_base(bank);
unsigned long clock = stm32_get_gpio_bank_clock(bank);
@ -211,41 +233,42 @@ void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t speed,
clk_enable(clock);
mmio_clrbits_32(base + GPIO_MODE_OFFSET,
((uint32_t)GPIO_MODE_MASK << (pin << 1)));
mmio_setbits_32(base + GPIO_MODE_OFFSET,
(mode & ~GPIO_OPEN_DRAIN) << (pin << 1));
mmio_clrsetbits_32(base + GPIO_MODE_OFFSET,
(uint32_t)GPIO_MODE_MASK << (pin << 1),
mode << (pin << 1));
if ((mode & GPIO_OPEN_DRAIN) != 0U) {
mmio_setbits_32(base + GPIO_TYPE_OFFSET, BIT(pin));
} else {
mmio_clrbits_32(base + GPIO_TYPE_OFFSET, BIT(pin));
}
mmio_clrsetbits_32(base + GPIO_TYPE_OFFSET,
(uint32_t)GPIO_TYPE_MASK << pin,
type << pin);
mmio_clrbits_32(base + GPIO_SPEED_OFFSET,
((uint32_t)GPIO_SPEED_MASK << (pin << 1)));
mmio_setbits_32(base + GPIO_SPEED_OFFSET, speed << (pin << 1));
mmio_clrsetbits_32(base + GPIO_SPEED_OFFSET,
(uint32_t)GPIO_SPEED_MASK << (pin << 1),
speed << (pin << 1));
mmio_clrbits_32(base + GPIO_PUPD_OFFSET,
((uint32_t)GPIO_PULL_MASK << (pin << 1)));
mmio_setbits_32(base + GPIO_PUPD_OFFSET, pull << (pin << 1));
mmio_clrsetbits_32(base + GPIO_PUPD_OFFSET,
(uint32_t)GPIO_PULL_MASK << (pin << 1),
pull << (pin << 1));
if (pin < GPIO_ALT_LOWER_LIMIT) {
mmio_clrbits_32(base + GPIO_AFRL_OFFSET,
((uint32_t)GPIO_ALTERNATE_MASK << (pin << 2)));
mmio_setbits_32(base + GPIO_AFRL_OFFSET,
alternate << (pin << 2));
mmio_clrsetbits_32(base + GPIO_AFRL_OFFSET,
(uint32_t)GPIO_ALTERNATE_MASK << (pin << 2),
alternate << (pin << 2));
} else {
mmio_clrbits_32(base + GPIO_AFRH_OFFSET,
((uint32_t)GPIO_ALTERNATE_MASK <<
((pin - GPIO_ALT_LOWER_LIMIT) << 2)));
mmio_setbits_32(base + GPIO_AFRH_OFFSET,
alternate << ((pin - GPIO_ALT_LOWER_LIMIT) <<
2));
size_t shift = (pin - GPIO_ALT_LOWER_LIMIT) << 2;
mmio_clrsetbits_32(base + GPIO_AFRH_OFFSET,
(uint32_t)GPIO_ALTERNATE_MASK << shift,
alternate << shift);
}
mmio_clrsetbits_32(base + GPIO_OD_OFFSET,
(uint32_t)GPIO_OD_MASK << pin,
od << pin);
VERBOSE("GPIO %u mode set to 0x%x\n", bank,
mmio_read_32(base + GPIO_MODE_OFFSET));
VERBOSE("GPIO %u type set to 0x%x\n", bank,
mmio_read_32(base + GPIO_TYPE_OFFSET));
VERBOSE("GPIO %u speed set to 0x%x\n", bank,
mmio_read_32(base + GPIO_SPEED_OFFSET));
VERBOSE("GPIO %u mode pull to 0x%x\n", bank,
@ -254,16 +277,22 @@ void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t speed,
mmio_read_32(base + GPIO_AFRL_OFFSET));
VERBOSE("GPIO %u mode alternate high to 0x%x\n", bank,
mmio_read_32(base + GPIO_AFRH_OFFSET));
VERBOSE("GPIO %u output data set to 0x%x\n", bank,
mmio_read_32(base + GPIO_OD_OFFSET));
clk_disable(clock);
if (status == DT_SECURE) {
stm32mp_register_secure_gpio(bank, pin);
#if !IMAGE_BL2
set_gpio_secure_cfg(bank, pin, true);
#endif
} else {
stm32mp_register_non_secure_gpio(bank, pin);
#if !IMAGE_BL2
set_gpio_secure_cfg(bank, pin, false);
#endif
}
}
@ -287,7 +316,8 @@ void set_gpio_secure_cfg(uint32_t bank, uint32_t pin, bool secure)
void set_gpio_reset_cfg(uint32_t bank, uint32_t pin)
{
set_gpio(bank, pin, GPIO_MODE_ANALOG, GPIO_SPEED_LOW,
GPIO_NO_PULL, GPIO_ALTERNATE_(0), DT_DISABLED);
set_gpio(bank, pin, GPIO_MODE_ANALOG, GPIO_TYPE_PUSH_PULL,
GPIO_SPEED_LOW, GPIO_NO_PULL, GPIO_OD_OUTPUT_LOW,
GPIO_ALTERNATE_(0), DT_DISABLED);
set_gpio_secure_cfg(bank, pin, stm32_gpio_is_secure_at_reset(bank));
}

35
include/drivers/st/stm32_gpio.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2021, STMicroelectronics - All Rights Reserved
* Copyright (c) 2015-2022, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -13,6 +13,7 @@
#define GPIO_TYPE_OFFSET U(0x04)
#define GPIO_SPEED_OFFSET U(0x08)
#define GPIO_PUPD_OFFSET U(0x0C)
#define GPIO_OD_OFFSET U(0x14)
#define GPIO_BSRR_OFFSET U(0x18)
#define GPIO_AFRL_OFFSET U(0x20)
#define GPIO_AFRH_OFFSET U(0x24)
@ -26,31 +27,35 @@
#define GPIO_ALTERNATE_(_x) U(_x)
#define GPIO_ALTERNATE_MASK U(0x0F)
#define GPIO_MODE_INPUT 0x00
#define GPIO_MODE_OUTPUT 0x01
#define GPIO_MODE_ALTERNATE 0x02
#define GPIO_MODE_ANALOG 0x03
#define GPIO_MODE_INPUT U(0x00)
#define GPIO_MODE_OUTPUT U(0x01)
#define GPIO_MODE_ALTERNATE U(0x02)
#define GPIO_MODE_ANALOG U(0x03)
#define GPIO_MODE_MASK U(0x03)
#define GPIO_OPEN_DRAIN U(0x10)
#define GPIO_TYPE_PUSH_PULL U(0x00)
#define GPIO_TYPE_OPEN_DRAIN U(0x01)
#define GPIO_TYPE_MASK U(0x01)
#define GPIO_SPEED_LOW 0x00
#define GPIO_SPEED_MEDIUM 0x01
#define GPIO_SPEED_HIGH 0x02
#define GPIO_SPEED_VERY_HIGH 0x03
#define GPIO_SPEED_LOW U(0x00)
#define GPIO_SPEED_MEDIUM U(0x01)
#define GPIO_SPEED_HIGH U(0x02)
#define GPIO_SPEED_VERY_HIGH U(0x03)
#define GPIO_SPEED_MASK U(0x03)
#define GPIO_NO_PULL 0x00
#define GPIO_PULL_UP 0x01
#define GPIO_PULL_DOWN 0x02
#define GPIO_NO_PULL U(0x00)
#define GPIO_PULL_UP U(0x01)
#define GPIO_PULL_DOWN U(0x02)
#define GPIO_PULL_MASK U(0x03)
#define GPIO_OD_OUTPUT_LOW U(0x00)
#define GPIO_OD_OUTPUT_HIGH U(0x01)
#define GPIO_OD_MASK U(0x01)
#ifndef __ASSEMBLER__
#include <stdint.h>
int dt_set_pinctrl_config(int node);
void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t speed,
uint32_t pull, uint32_t alternate, uint8_t status);
void set_gpio_secure_cfg(uint32_t bank, uint32_t pin, bool secure);
void set_gpio_reset_cfg(uint32_t bank, uint32_t pin);
#endif /*__ASSEMBLER__*/

21
plat/st/common/stm32mp_dt.c
View File

@ -404,6 +404,9 @@ int fdt_get_gpio_bank_pin_count(unsigned int bank)
fdt_for_each_subnode(node, fdt, pinctrl_node) {
const fdt32_t *cuint;
int pin_count;
int len;
int i;
if (fdt_getprop(fdt, node, "gpio-controller", NULL) == NULL) {
continue;
@ -422,12 +425,22 @@ int fdt_get_gpio_bank_pin_count(unsigned int bank)
return 0;
}
cuint = fdt_getprop(fdt, node, "ngpios", NULL);
if (cuint == NULL) {
return -FDT_ERR_NOTFOUND;
/* Parse gpio-ranges with its 4 parameters */
cuint = fdt_getprop(fdt, node, "gpio-ranges", &len);
len /= sizeof(*cuint);
if ((len % 4) != 0) {
return -FDT_ERR_BADVALUE;
}
/* Get the last defined gpio line (offset + nb of pins) */
pin_count = fdt32_to_cpu(*(cuint + 1)) + fdt32_to_cpu(*(cuint + 3));
for (i = 0; i < len / 4; i++) {
pin_count = MAX(pin_count, (int)(fdt32_to_cpu(*(cuint + 1)) +
fdt32_to_cpu(*(cuint + 3))));
cuint += 4;
}
return (int)fdt32_to_cpu(*cuint);
return pin_count;
}
return 0;

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