From f2596ff1a8c0c3daddcd406a18224fce9af0f1fc Mon Sep 17 00:00:00 2001 From: Boyan Karatotev Date: Fri, 19 Apr 2024 12:27:46 +0100 Subject: [PATCH] feat(tc): bind SCMI over MHUv3 for TC3 TC2 and TC3 have different the scmi shared memory regions and MHU parameters, this patch appends the properties in scmi node for TC2 and TC3 respectively. Change-Id: Ifd001f780b575987877b4be36eb755a9dbe57e60 Signed-off-by: Boyan Karatotev Signed-off-by: Leo Yan --- fdts/tc-base.dtsi | 4 +--- fdts/tc2.dts | 18 ++++++++++++++++++ fdts/tc3.dts | 14 ++++++++++++++ 3 files changed, 33 insertions(+), 3 deletions(-) diff --git a/fdts/tc-base.dtsi b/fdts/tc-base.dtsi index 670630e3b..949105fb1 100644 --- a/fdts/tc-base.dtsi +++ b/fdts/tc-base.dtsi @@ -278,7 +278,7 @@ #size-cells = <1>; ranges = <0 0x0 PLAT_ARM_NSRAM_BASE PLAT_ARM_NSRAM_SIZE>; - cpu_scp_scmi_mem: scp-shmem@0 { + cpu_scp_scmi_a2p: scp-shmem@0 { compatible = "arm,scmi-shmem"; reg = <0x0 0x80>; }; @@ -307,8 +307,6 @@ scmi { compatible = "arm,scmi"; mbox-names = "tx", "rx"; - mboxes = <&mbox_db_tx 0 0 &mbox_db_rx 0 0 >; - shmem = <&cpu_scp_scmi_mem &cpu_scp_scmi_mem>; #address-cells = <1>; #size-cells = <0>; diff --git a/fdts/tc2.dts b/fdts/tc2.dts index 2cdfc6ba6..69c688601 100644 --- a/fdts/tc2.dts +++ b/fdts/tc2.dts @@ -219,6 +219,24 @@ arm,mhuv2-protocols = <0 1>; }; + firmware { + /* + * TC2 does not have a P2A channel, but wiring one was needed to make Linux work + * (by chance). At the time the SCMI driver did not support bidirectional + * mailboxes so as a workaround, the A2P channel was wired for TX communication + * and the synchronous replies would be read asyncrhonously as if coming from + * the P2A channel, while being the actual A2P channel. + * + * This will not work with kernels > 5.15, but keep it around to keep TC2 + * working with its target kernel. Newer kernels will still work, but SCMI + * won't as they check that the two regions are distinct. + */ + scmi { + mboxes = <&mbox_db_tx 0 0 &mbox_db_rx 0 0>; + shmem = <&cpu_scp_scmi_a2p &cpu_scp_scmi_a2p>; + }; + }; + dp0: display@DPU_ADDR { #if TC_SCMI_PD_CTRL_EN power-domains = <&scmi_devpd (PLAT_MAX_CPUS_PER_CLUSTER + 2)>; diff --git a/fdts/tc3.dts b/fdts/tc3.dts index fa4bed74a..fe6a69562 100644 --- a/fdts/tc3.dts +++ b/fdts/tc3.dts @@ -71,4 +71,18 @@ interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>, <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>; }; + + sram: sram@6000000 { + cpu_scp_scmi_p2a: scp-shmem@80 { + compatible = "arm,scmi-shmem"; + reg = <0x80 0x80>; + }; + }; + + firmware { + scmi { + mboxes = <&mbox_db_tx 0 0 0 &mbox_db_rx 0 0 0 &mbox_db_rx 0 0 1>; + shmem = <&cpu_scp_scmi_a2p &cpu_scp_scmi_p2a>; + }; + }; };