rcar_gen3: drivers: ddr_b: Fix checkpatch errors in headers

Clean up the DDR B header files and remove checkpatch errors.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I9648ef5511df299688fd5284513812d32a1f8064

drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h

@@ -1,13 +1,14 @@
 /*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation.
+ * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #define RCAR_DDR_VERSION	"rev.0.36"
-#define DRAM_CH_CNT		(0x04)
-#define SLICE_CNT		(0x04)
-#define CS_CNT			(0x02)
+#define DRAM_CH_CNT		0x04
+#define SLICE_CNT		0x04
+#define CS_CNT			0x02
 
 /* order : CS0A, CS0B, CS1A, CS1B */
 #define CSAB_CNT		(CS_CNT * 2)
@@ -24,7 +25,8 @@
 	((d3) << 30 | ((row) << 24) | ((bank) << 16) | ((col) << 8) | (dw))
 
 #define DBMEMCONF_REGD(density)		\
-(DBMEMCONF_REG((density) % 2, ((density) + 1) / 2 + (29-3-10-2), 3, 10, 2))
+	(DBMEMCONF_REG((density) % 2, ((density) + 1) / \
+	2 + (29 - 3 - 10 - 2), 3, 10, 2))
 
 #define DBMEMCONF_VAL(ch, cs) (DBMEMCONF_REGD(DBMEMCONF_DENS(ch, cs)))
 
@@ -44,10 +46,10 @@
 #define CPG_CPGWPR		(CPG_BASE + 0x0900U)
 #define CPG_SRSTCLR4		(CPG_BASE + 0x0950U)
 
-#define CPG_FRQCRB_KICK_BIT	(1U<<31)
-#define CPG_PLLECR_PLL3E_BIT	(1U<<3)
-#define CPG_PLLECR_PLL3ST_BIT	(1U<<11)
-#define CPG_ZB3CKCR_ZB3ST_BIT	(1U<<11)
+#define CPG_FRQCRB_KICK_BIT	BIT(31)
+#define CPG_PLLECR_PLL3E_BIT	BIT(3)
+#define CPG_PLLECR_PLL3ST_BIT	BIT(11)
+#define CPG_ZB3CKCR_ZB3ST_BIT	BIT(11)
 
 #define RST_BASE		(0xE6160000U)
 #define RST_MODEMR		(RST_BASE + 0x0060U)

drivers/staging/renesas/rcar/ddr/ddr_b/ddr_regdef.h

@@ -1,5 +1,6 @@
 /*
- * Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2018-2019, Renesas Electronics Corporation.
+ * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */

drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h

@@ -1,5 +1,6 @@
 /*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation.
+ * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */

drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h

@@ -1,5 +1,6 @@
 /*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation.
+ * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -22,8 +23,8 @@
 #define DDR_PHY_ADR_G_REGSET_NUM_H3VER2  79
 #define DDR_PI_REGSET_NUM_H3VER2         245
 
-static const uint32_t
-    DDR_PHY_SLICE_REGSET_H3VER2[DDR_PHY_SLICE_REGSET_NUM_H3VER2] = {
+static const uint32_t DDR_PHY_SLICE_REGSET_H3VER2
+	[DDR_PHY_SLICE_REGSET_NUM_H3VER2] = {
 	/*0400*/ 0x76543210,
 	/*0401*/ 0x0004f008,
 	/*0402*/ 0x00020133,

drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h

@@ -1,5 +1,6 @@
 /*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation.
+ * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */

drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h

@@ -1,5 +1,6 @@
 /*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation.
+ * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */