diff --git a/changelog.yaml b/changelog.yaml index 4d38e37ec..fa42e968a 100644 --- a/changelog.yaml +++ b/changelog.yaml @@ -185,6 +185,13 @@ subsections: deprecated: - plat/tc0 + - title: Intel + scope: intel + + subsections: + - title: SoC + scope: soc + - title: Marvell scope: marvell diff --git a/plat/intel/soc/common/include/socfpga_mailbox.h b/plat/intel/soc/common/include/socfpga_mailbox.h index 39662e21f..bc10dd883 100644 --- a/plat/intel/soc/common/include/socfpga_mailbox.h +++ b/plat/intel/soc/common/include/socfpga_mailbox.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020, Intel Corporation. All rights reserved. + * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -69,6 +69,7 @@ #define CMD_CASUAL 0 #define CMD_URGENT 1 +#define MBOX_WORD_BYTE 4U #define MBOX_RESP_BUFFER_SIZE 16 #define MBOX_CMD_BUFFER_SIZE 32 @@ -108,6 +109,9 @@ /* Mailbox Macros */ +#define MBOX_ENTRY_TO_ADDR(_buf, ptr) (MBOX_OFFSET + (MBOX_##_buf##_BUFFER) \ + + MBOX_WORD_BYTE * (ptr)) + /* Mailbox interrupt flags and masks */ #define MBOX_INT_FLAG_COE 0x1 #define MBOX_INT_FLAG_RIE 0x2 @@ -143,18 +147,18 @@ void mailbox_hps_qspi_enable(void); int mailbox_send_cmd(uint32_t job_id, uint32_t cmd, uint32_t *args, unsigned int len, uint32_t urgent, uint32_t *response, - unsigned int resp_len); + unsigned int *resp_len); int mailbox_send_cmd_async(uint32_t *job_id, uint32_t cmd, uint32_t *args, unsigned int len, unsigned int indirect); int mailbox_read_response(uint32_t *job_id, uint32_t *response, - unsigned int resp_len); -unsigned int iterate_resp(uint32_t mbox_resp_len, uint32_t *resp_buf, - unsigned int resp_len); + unsigned int *resp_len); +int iterate_resp(uint32_t mbox_resp_len, uint32_t *resp_buf, + unsigned int *resp_len); void mailbox_reset_cold(void); void mailbox_clear_response(void); -int intel_mailbox_get_config_status(uint32_t cmd); +int intel_mailbox_get_config_status(uint32_t cmd, bool init_done); int intel_mailbox_is_fpga_not_ready(void); int mailbox_rsu_get_spt_offset(uint32_t *resp_buf, uint32_t resp_buf_len); diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c index 34508a876..be900c967 100644 --- a/plat/intel/soc/common/soc/socfpga_mailbox.c +++ b/plat/intel/soc/common/soc/socfpga_mailbox.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, Intel Corporation. All rights reserved. + * Copyright (c) 2020-2022, Intel Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -59,9 +59,7 @@ static int write_mailbox_cmd_buffer(uint32_t *cin, uint32_t cout, } mdelay(10U); } else { - mmio_write_32(MBOX_OFFSET + MBOX_CMD_BUFFER + - (*cin * 4), data); - (*cin)++; + mmio_write_32(MBOX_ENTRY_TO_ADDR(CMD, (*cin)++), data); *cin %= MBOX_CMD_BUFFER_SIZE; mmio_write_32(MBOX_OFFSET + MBOX_CIN, *cin); break; @@ -107,9 +105,7 @@ static int fill_mailbox_circular_buffer(uint32_t header_cmd, uint32_t *args, } } - if (!is_doorbell_triggered) { - mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_TO_SDM, 1U); - } + mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_TO_SDM, 1U); return MBOX_RET_OK; @@ -131,7 +127,7 @@ restart_mailbox: } int mailbox_read_response(unsigned int *job_id, uint32_t *response, - unsigned int resp_len) + unsigned int *resp_len) { uint32_t rin; uint32_t rout; @@ -146,8 +142,7 @@ int mailbox_read_response(unsigned int *job_id, uint32_t *response, rout = mmio_read_32(MBOX_OFFSET + MBOX_ROUT); if (rout != rin) { - resp_data = mmio_read_32(MBOX_OFFSET + - MBOX_RESP_BUFFER + ((rout++)*4U)); + resp_data = mmio_read_32(MBOX_ENTRY_TO_ADDR(RESP, (rout)++)); rout %= MBOX_RESP_BUFFER_SIZE; mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout); @@ -161,9 +156,9 @@ int mailbox_read_response(unsigned int *job_id, uint32_t *response, ret_resp_len = MBOX_RESP_LEN(resp_data); - if (ret_resp_len != 0U) { - ret_resp_len = iterate_resp(ret_resp_len, response, - resp_len); + if (iterate_resp(ret_resp_len, response, resp_len) + != MBOX_RET_OK) { + return MBOX_TIMEOUT; } if (MBOX_RESP_ERR(resp_data) > 0U) { @@ -171,14 +166,14 @@ int mailbox_read_response(unsigned int *job_id, uint32_t *response, return -MBOX_RESP_ERR(resp_data); } - return ret_resp_len; + return MBOX_RET_OK; } return MBOX_NO_RESPONSE; } int mailbox_poll_response(uint32_t job_id, uint32_t urgent, uint32_t *response, - unsigned int resp_len) + unsigned int *resp_len) { unsigned int timeout = 40U; unsigned int sdm_loop = 255U; @@ -221,8 +216,8 @@ int mailbox_poll_response(uint32_t job_id, uint32_t urgent, uint32_t *response, rout = mmio_read_32(MBOX_OFFSET + MBOX_ROUT); while (rout != rin) { - resp_data = mmio_read_32(MBOX_OFFSET + - MBOX_RESP_BUFFER + ((rout++)*4U)); + resp_data = mmio_read_32(MBOX_ENTRY_TO_ADDR(RESP, + (rout)++)); rout %= MBOX_RESP_BUFFER_SIZE; mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout); @@ -234,10 +229,9 @@ int mailbox_poll_response(uint32_t job_id, uint32_t urgent, uint32_t *response, ret_resp_len = MBOX_RESP_LEN(resp_data); - if (ret_resp_len != 0U) { - ret_resp_len = iterate_resp(ret_resp_len, - response, - resp_len); + if (iterate_resp(ret_resp_len, response, resp_len) + != MBOX_RET_OK) { + return MBOX_TIMEOUT; } if (MBOX_RESP_ERR(resp_data) > 0U) { @@ -245,7 +239,7 @@ int mailbox_poll_response(uint32_t job_id, uint32_t urgent, uint32_t *response, return -MBOX_RESP_ERR(resp_data); } - return ret_resp_len; + return MBOX_RET_OK; } sdm_loop--; @@ -255,8 +249,8 @@ int mailbox_poll_response(uint32_t job_id, uint32_t urgent, uint32_t *response, return MBOX_TIMEOUT; } -unsigned int iterate_resp(uint32_t mbox_resp_len, uint32_t *resp_buf, - unsigned int resp_len) +int iterate_resp(uint32_t mbox_resp_len, uint32_t *resp_buf, + unsigned int *resp_len) { unsigned int timeout, total_resp_len = 0U; uint32_t resp_data; @@ -266,17 +260,15 @@ unsigned int iterate_resp(uint32_t mbox_resp_len, uint32_t *resp_buf, while (mbox_resp_len > 0U) { timeout = 100U; mbox_resp_len--; - resp_data = mmio_read_32(MBOX_OFFSET + - MBOX_RESP_BUFFER + - (rout)*4U); + resp_data = mmio_read_32(MBOX_ENTRY_TO_ADDR(RESP, (rout)++)); - if ((resp_buf != NULL) && (resp_len != 0U)) { + if ((resp_buf != NULL) && (resp_len != NULL) + && (*resp_len != 0U)) { *(resp_buf + total_resp_len) = resp_data; - resp_len--; + *resp_len = *resp_len - 1; total_resp_len++; } - rout++; rout %= MBOX_RESP_BUFFER_SIZE; mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout); @@ -295,7 +287,11 @@ unsigned int iterate_resp(uint32_t mbox_resp_len, uint32_t *resp_buf, return MBOX_TIMEOUT; } } - return total_resp_len; + + if (resp_len) + *resp_len = total_resp_len; + + return MBOX_RET_OK; } int mailbox_send_cmd_async(uint32_t *job_id, uint32_t cmd, uint32_t *args, @@ -320,7 +316,7 @@ int mailbox_send_cmd_async(uint32_t *job_id, uint32_t cmd, uint32_t *args, int mailbox_send_cmd(uint32_t job_id, uint32_t cmd, uint32_t *args, unsigned int len, uint32_t urgent, uint32_t *response, - unsigned int resp_len) + unsigned int *resp_len) { int status = 0; @@ -366,20 +362,20 @@ void mailbox_set_qspi_open(void) { mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_OPEN, NULL, 0U, - CMD_CASUAL, NULL, 0U); + CMD_CASUAL, NULL, NULL); } void mailbox_set_qspi_direct(void) { mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_DIRECT, NULL, 0U, - CMD_CASUAL, NULL, 0U); + CMD_CASUAL, NULL, NULL); } void mailbox_set_qspi_close(void) { mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_CLOSE, NULL, 0U, - CMD_CASUAL, NULL, 0U); + CMD_CASUAL, NULL, NULL); } void mailbox_qspi_set_cs(uint32_t device_select) @@ -390,7 +386,7 @@ void mailbox_qspi_set_cs(uint32_t device_select) cs_setting = (device_select << 28); mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_SET_CS, &cs_setting, - 1U, CMD_CASUAL, NULL, 0U); + 1U, CMD_CASUAL, NULL, NULL); } void mailbox_hps_qspi_enable(void) @@ -403,14 +399,14 @@ void mailbox_reset_cold(void) { mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_REBOOT_HPS, NULL, 0U, - CMD_CASUAL, NULL, 0U); + CMD_CASUAL, NULL, NULL); } int mailbox_rsu_get_spt_offset(uint32_t *resp_buf, unsigned int resp_buf_len) { return mailbox_send_cmd(MBOX_JOB_ID, MBOX_GET_SUBPARTITION_TABLE, NULL, 0U, CMD_CASUAL, resp_buf, - resp_buf_len); + &resp_buf_len); } struct rsu_status_info { @@ -432,7 +428,7 @@ int mailbox_rsu_status(uint32_t *resp_buf, unsigned int resp_buf_len) ret = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RSU_STATUS, NULL, 0U, CMD_CASUAL, resp_buf, - resp_buf_len); + &resp_buf_len); if (ret < 0) { return ret; @@ -451,14 +447,14 @@ int mailbox_rsu_update(uint32_t *flash_offset) { return mailbox_send_cmd(MBOX_JOB_ID, MBOX_RSU_UPDATE, flash_offset, 2U, - CMD_CASUAL, NULL, 0U); + CMD_CASUAL, NULL, NULL); } int mailbox_hps_stage_notify(uint32_t execution_stage) { return mailbox_send_cmd(MBOX_JOB_ID, MBOX_HPS_STAGE_NOTIFY, &execution_stage, 1U, CMD_CASUAL, - NULL, 0U); + NULL, NULL); } int mailbox_init(void) @@ -471,7 +467,7 @@ int mailbox_init(void) mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0U); status = mailbox_send_cmd(0U, MBOX_CMD_RESTART, NULL, 0U, - CMD_URGENT, NULL, 0U); + CMD_URGENT, NULL, NULL); if (status != 0) { return status; @@ -483,13 +479,14 @@ int mailbox_init(void) return MBOX_RET_OK; } -int intel_mailbox_get_config_status(uint32_t cmd) +int intel_mailbox_get_config_status(uint32_t cmd, bool init_done) { int status; uint32_t res, response[6]; + unsigned int resp_len = ARRAY_SIZE(response); status = mailbox_send_cmd(MBOX_JOB_ID, cmd, NULL, 0U, CMD_CASUAL, - response, ARRAY_SIZE(response)); + response, &resp_len); if (status < 0) { return status; @@ -510,20 +507,22 @@ int intel_mailbox_get_config_status(uint32_t cmd) return MBOX_CFGSTAT_STATE_ERROR_HARDWARE; } - if ((res & SOFTFUNC_STATUS_CONF_DONE) != 0U && - (res & SOFTFUNC_STATUS_INIT_DONE) != 0U) { - return MBOX_RET_OK; - } + if ((res & SOFTFUNC_STATUS_CONF_DONE) == 0U) + return MBOX_CFGSTAT_STATE_CONFIG; - return MBOX_CFGSTAT_STATE_CONFIG; + if (init_done && (res & SOFTFUNC_STATUS_INIT_DONE) == 0U) + return MBOX_CFGSTAT_STATE_CONFIG; + + return MBOX_RET_OK; } int intel_mailbox_is_fpga_not_ready(void) { - int ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS); + int ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, true); if ((ret != MBOX_RET_OK) && (ret != MBOX_CFGSTAT_STATE_CONFIG)) { - ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS); + ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS, + false); } return ret; diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c index 86a44556a..d53e8deb5 100644 --- a/plat/intel/soc/common/socfpga_sip_svc.c +++ b/plat/intel/soc/common/socfpga_sip_svc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -83,9 +83,9 @@ static uint32_t intel_mailbox_fpga_config_isdone(uint32_t query_type) uint32_t ret; if (query_type == 1) - ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS); + ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS, false); else - ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS); + ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, true); if (ret) { if (ret == MBOX_CFGSTAT_STATE_CONFIG) @@ -128,16 +128,16 @@ static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed) static int intel_fpga_config_completed_write(uint32_t *completed_addr, uint32_t *count, uint32_t *job_id) { - uint32_t status = INTEL_SIP_SMC_STATUS_OK; - *count = 0; - int resp_len = 0; uint32_t resp[5]; + unsigned int resp_len = ARRAY_SIZE(resp); + int status = INTEL_SIP_SMC_STATUS_OK; int all_completed = 1; + *count = 0; while (*count < 3) { - resp_len = mailbox_read_response(job_id, - resp, ARRAY_SIZE(resp)); + status = mailbox_read_response(job_id, + resp, &resp_len); if (resp_len < 0) break; @@ -183,17 +183,21 @@ static int intel_fpga_config_completed_write(uint32_t *completed_addr, static int intel_fpga_config_start(uint32_t config_type) { + uint32_t argument = 0x1; uint32_t response[3]; int status = 0; + unsigned int size = 0; + unsigned int resp_len = ARRAY_SIZE(response); is_partial_reconfig = config_type; mailbox_clear_response(); - mailbox_send_cmd(1U, MBOX_CMD_CANCEL, NULL, 0U, CMD_CASUAL, NULL, 0U); + mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_CANCEL, NULL, 0U, + CMD_CASUAL, NULL, NULL); - status = mailbox_send_cmd(1U, MBOX_RECONFIG, NULL, 0U, CMD_CASUAL, - response, ARRAY_SIZE(response)); + status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RECONFIG, &argument, size, + CMD_CASUAL, response, &resp_len); if (status < 0) return status; @@ -234,6 +238,9 @@ static bool is_fpga_config_buffer_full(void) bool is_address_in_ddr_range(uint64_t addr, uint64_t size) { + if (!addr && !size) { + return true; + } if (size > (UINT64_MAX - addr)) return false; if (addr < BL31_LIMIT) @@ -341,7 +348,7 @@ uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask, { if (!intel_secure_reg_read(reg_addr, retval)) { *retval &= ~mask; - *retval |= val; + *retval |= val & mask; return intel_secure_reg_write(reg_addr, *retval, retval); } @@ -384,10 +391,11 @@ static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz, } /* Mailbox services */ -static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, uint32_t len, - uint32_t urgent, uint32_t *response, - uint32_t resp_len, int *mbox_status, - int *len_in_resp) +static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, + unsigned int len, + uint32_t urgent, uint32_t *response, + unsigned int resp_len, int *mbox_status, + unsigned int *len_in_resp) { *len_in_resp = 0; *mbox_status = 0; @@ -396,7 +404,7 @@ static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, uint32_t len, return INTEL_SIP_SMC_STATUS_REJECTED; int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent, - response, resp_len); + response, &resp_len); if (status < 0) { *mbox_status = -status; @@ -404,7 +412,7 @@ static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, uint32_t len, } *mbox_status = 0; - *len_in_resp = status; + *len_in_resp = resp_len; return INTEL_SIP_SMC_STATUS_OK; } @@ -425,9 +433,9 @@ uintptr_t sip_smc_handler(uint32_t smc_fid, uint32_t status = INTEL_SIP_SMC_STATUS_OK; uint32_t completed_addr[3]; uint64_t rsu_respbuf[9]; + int mbox_status; + unsigned int len_in_resp; u_register_t x5, x6; - int mbox_status, len_in_resp; - switch (smc_fid) { case SIP_SVC_UID: @@ -525,7 +533,7 @@ uintptr_t sip_smc_handler(uint32_t smc_fid, status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4, (uint32_t *)x5, x6, &mbox_status, &len_in_resp); - SMC_RET4(handle, status, mbox_status, x5, len_in_resp); + SMC_RET3(handle, status, mbox_status, len_in_resp); default: return socfpga_sip_handler(smc_fid, x1, x2, x3, x4,