From fa37d30856fef6742bd82e4e0a3252a4d0b9e091 Mon Sep 17 00:00:00 2001 From: Joshua Pimm Date: Wed, 19 Oct 2022 15:46:27 +0100 Subject: [PATCH] feat(ethos-n): add reset type to reset SMC calls Adds a reset type argument for the soft and hard reset SMC calls to indicate whether to perform a full reset and setup or only halt the Arm(R) Ethos(TM)-N NPU. For use in cases where the NPU will not be used but must be put into a known state, such as suspending the NPU as part of power management. Signed-off-by: Joshua Pimm Signed-off-by: Mikael Olsson Change-Id: I6018af85a28b0e977166ec29d26f04739123140c --- drivers/arm/ethosn/ethosn_smc.c | 28 +++++++++++++++++++--------- include/drivers/arm/ethosn.h | 15 +++++++++++---- 2 files changed, 30 insertions(+), 13 deletions(-) diff --git a/drivers/arm/ethosn/ethosn_smc.c b/drivers/arm/ethosn/ethosn_smc.c index 915a0d87a..c95c22ce5 100644 --- a/drivers/arm/ethosn/ethosn_smc.c +++ b/drivers/arm/ethosn/ethosn_smc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022, Arm Limited. All rights reserved. + * Copyright (c) 2021-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -152,7 +152,7 @@ static bool ethosn_reset(uintptr_t core_addr, int hard_reset) uintptr_t ethosn_smc_handler(uint32_t smc_fid, u_register_t core_addr, u_register_t asset_alloc_idx, - u_register_t x3, + u_register_t reset_type, u_register_t x4, void *cookie, void *handle, @@ -173,7 +173,7 @@ uintptr_t ethosn_smc_handler(uint32_t smc_fid, if (GET_SMC_CC(smc_fid) == SMC_32) { core_addr &= 0xFFFFFFFF; asset_alloc_idx &= 0xFFFFFFFF; - x3 &= 0xFFFFFFFF; + reset_type &= 0xFFFFFFFF; x4 &= 0xFFFFFFFF; } @@ -205,7 +205,15 @@ uintptr_t ethosn_smc_handler(uint32_t smc_fid, SMC_RET1(handle, ETHOSN_UNKNOWN_ALLOCATOR_IDX); } - /* Commands that require a valid device, core and asset allocator */ + if (reset_type > ETHOSN_RESET_TYPE_HALT) { + WARN("ETHOSN: Invalid reset type given to SMC call.\n"); + SMC_RET1(handle, ETHOSN_INVALID_PARAMETER); + } + + /* + * Commands that require a valid device, reset type, + * core and asset allocator + */ switch (fid) { case ETHOSN_FNUM_HARD_RESET: hard_reset = 1; @@ -215,12 +223,14 @@ uintptr_t ethosn_smc_handler(uint32_t smc_fid, SMC_RET1(handle, ETHOSN_FAILURE); } - if (!device->has_reserved_memory) { - ethosn_configure_smmu_streams(device, core, - asset_alloc_idx); - } + if (reset_type == ETHOSN_RESET_TYPE_FULL) { + if (!device->has_reserved_memory) { + ethosn_configure_smmu_streams(device, core, + asset_alloc_idx); + } - ethosn_delegate_to_ns(core->addr); + ethosn_delegate_to_ns(core->addr); + } SMC_RET1(handle, ETHOSN_SUCCESS); default: WARN("ETHOSN: Unimplemented SMC call: 0x%x\n", fid); diff --git a/include/drivers/arm/ethosn.h b/include/drivers/arm/ethosn.h index dbaf16cd7..ce7b2f30f 100644 --- a/include/drivers/arm/ethosn.h +++ b/include/drivers/arm/ethosn.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022, Arm Limited. All rights reserved. + * Copyright (c) 2021-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -39,21 +39,28 @@ /* Service version */ #define ETHOSN_VERSION_MAJOR U(2) -#define ETHOSN_VERSION_MINOR U(0) +#define ETHOSN_VERSION_MINOR U(1) /* Return codes for function calls */ #define ETHOSN_SUCCESS 0 #define ETHOSN_NOT_SUPPORTED -1 /* -2 Reserved for NOT_REQUIRED */ -/* -3 Reserved for INVALID_PARAMETER */ +#define ETHOSN_INVALID_PARAMETER -3 #define ETHOSN_FAILURE -4 #define ETHOSN_UNKNOWN_CORE_ADDRESS -5 #define ETHOSN_UNKNOWN_ALLOCATOR_IDX -6 +/* + * Argument types for soft and hard resets to indicate whether to reset + * and reconfigure the NPU or only halt it + */ +#define ETHOSN_RESET_TYPE_FULL U(0) +#define ETHOSN_RESET_TYPE_HALT U(1) + uintptr_t ethosn_smc_handler(uint32_t smc_fid, u_register_t core_addr, u_register_t asset_alloc_idx, - u_register_t x3, + u_register_t reset_type, u_register_t x4, void *cookie, void *handle,