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Merge changes from topic "xlnx_zynqmp_misra" into integration 

* changes:
  fix(zynqmp): resolve misra R14.4 warnings
  fix(zynqmp): resolve misra R16.3 warnings
  fix(zynqmp): resolve misra R15.7 warnings
  fix(zynqmp): resolve misra R15.6 warnings
  fix(zynqmp): resolve misra 7.2 warnings
  fix(zynqmp): resolve misra R10.3
pull/1985/head
Manish Pandey 3 years ago
committed by TrustedFirmware Code Review
parent
e8ad39759b dd1fe7178b
commit
fad4a7175b
15 changed files with 396 additions and 237 deletions
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  1. 18
      plat/xilinx/common/ipi.c
  2. 25
      plat/xilinx/common/plat_startup.c
  3. 23
      plat/xilinx/common/pm_service/pm_ipi.c
  4. 25
      plat/xilinx/zynqmp/aarch64/zynqmp_common.c
  5. 6
      plat/xilinx/zynqmp/bl31_zynqmp_setup.c
  6. 20
      plat/xilinx/zynqmp/include/platform_def.h
  7. 30
      plat/xilinx/zynqmp/include/zynqmp_def.h
  8. 28
      plat/xilinx/zynqmp/plat_psci.c
  9. 120
      plat/xilinx/zynqmp/pm_service/pm_api_clock.c
  10. 133
      plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c
  11. 44
      plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c
  12. 104
      plat/xilinx/zynqmp/pm_service/pm_api_sys.c
  13. 27
      plat/xilinx/zynqmp/pm_service/pm_client.c
  14. 8
      plat/xilinx/zynqmp/sip_svc_setup.c
  15. 22
      plat/xilinx/zynqmp/zynqmp_ipi.c

18
plat/xilinx/common/ipi.c
View File

@ -69,8 +69,9 @@ static inline int is_ipi_mb_within_range(uint32_t local, uint32_t remote)
{
int ret = 1;
if (remote >= ipi_total || local >= ipi_total)
if (remote >= ipi_total || local >= ipi_total) {
ret = 0;
}
return ret;
}
@ -88,12 +89,15 @@ int ipi_mb_validate(uint32_t local, uint32_t remote, unsigned int is_secure)
{
int ret = 0;
if (!is_ipi_mb_within_range(local, remote))
if (!is_ipi_mb_within_range(local, remote)) {
ret = -EINVAL;
else if (IPI_IS_SECURE(local) && !is_secure)
} else if (IPI_IS_SECURE(local) && !is_secure) {
ret = -EPERM;
else if (IPI_IS_SECURE(remote) && !is_secure)
} else if (IPI_IS_SECURE(remote) && !is_secure) {
ret = -EPERM;
} else {
/* To fix the misra 15.7 warning */
}
return ret;
}
@ -141,11 +145,13 @@ int ipi_mb_enquire_status(uint32_t local, uint32_t remote)
uint32_t status;
status = mmio_read_32(IPI_REG_BASE(local) + IPI_OBR_OFFSET);
if (status & IPI_BIT_MASK(remote))
if (status & IPI_BIT_MASK(remote)) {
ret |= IPI_MB_STATUS_SEND_PENDING;
}
status = mmio_read_32(IPI_REG_BASE(local) + IPI_ISR_OFFSET);
if (status & IPI_BIT_MASK(remote))
if (status & IPI_BIT_MASK(remote)) {
ret |= IPI_MB_STATUS_RECV_PENDING;
}
return ret;
}

25
plat/xilinx/common/plat_startup.c
View File

@ -123,10 +123,11 @@ static int get_fsbl_endian(const struct xfsbl_partition *partition)
flags >>= FSBL_FLAGS_ENDIAN_SHIFT;
if (flags == FSBL_FLAGS_ENDIAN_BE)
if (flags == FSBL_FLAGS_ENDIAN_BE) {
return SPSR_E_BIG;
else
} else {
return SPSR_E_LITTLE;
}
}
/**
@ -226,30 +227,33 @@ enum fsbl_handoff fsbl_atf_handover(entry_point_info_t *bl32,
if (target_secure == FSBL_FLAGS_SECURE) {
image = bl32;
if (target_estate == FSBL_FLAGS_ESTATE_A32)
if (target_estate == FSBL_FLAGS_ESTATE_A32) {
bl32->spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM,
target_endianness,
DISABLE_ALL_EXCEPTIONS);
else
} else {
bl32->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX,
DISABLE_ALL_EXCEPTIONS);
}
} else {
image = bl33;
if (target_estate == FSBL_FLAGS_ESTATE_A32) {
if (target_el == FSBL_FLAGS_EL2)
if (target_el == FSBL_FLAGS_EL2) {
target_el = MODE32_hyp;
else
} else {
target_el = MODE32_sys;
}
bl33->spsr = SPSR_MODE32(target_el, SPSR_T_ARM,
target_endianness,
DISABLE_ALL_EXCEPTIONS);
} else {
if (target_el == FSBL_FLAGS_EL2)
if (target_el == FSBL_FLAGS_EL2) {
target_el = MODE_EL2;
else
} else {
target_el = MODE_EL1;
}
bl33->spsr = SPSR_64(target_el, MODE_SP_ELX,
DISABLE_ALL_EXCEPTIONS);
@ -262,10 +266,11 @@ enum fsbl_handoff fsbl_atf_handover(entry_point_info_t *bl32,
target_el);
image->pc = ATFHandoffParams->partition[i].entry_point;
if (target_endianness == SPSR_E_BIG)
if (target_endianness == SPSR_E_BIG) {
EP_SET_EE(image->h.attr, EP_EE_BIG);
else
} else {
EP_SET_EE(image->h.attr, EP_EE_LITTLE);
}
}
return FSBL_HANDOFF_SUCCESS;

23
plat/xilinx/common/pm_service/pm_ipi.c
View File

@ -154,14 +154,16 @@ static enum pm_ret_status pm_ipi_buff_read(const struct pm_proc *proc,
value++;
}
#if IPI_CRC_CHECK
for (j = 0; j < PAYLOAD_ARG_CNT; j++)
for (j = 0; j < PAYLOAD_ARG_CNT; j++) {
response_payload[j] = mmio_read_32(buffer_base +
(j * PAYLOAD_ARG_SIZE));
}
if (response_payload[PAYLOAD_CRC_POS] !=
calculate_crc(response_payload, IPI_W0_TO_W6_SIZE))
calculate_crc(response_payload, IPI_W0_TO_W6_SIZE)) {
NOTICE("ERROR in CRC response payload value:0x%x\n",
response_payload[PAYLOAD_CRC_POS]);
}
#endif
return mmio_read_32(buffer_base);
@ -186,22 +188,25 @@ void pm_ipi_buff_read_callb(unsigned int *value, size_t count)
IPI_BUFFER_TARGET_LOCAL_OFFSET +
IPI_BUFFER_REQ_OFFSET;
if (count > IPI_BUFFER_MAX_WORDS)
if (count > IPI_BUFFER_MAX_WORDS) {
count = IPI_BUFFER_MAX_WORDS;
}
for (i = 0; i <= count; i++) {
*value = mmio_read_32(buffer_base + (i * PAYLOAD_ARG_SIZE));
value++;
}
#if IPI_CRC_CHECK
for (j = 0; j < PAYLOAD_ARG_CNT; j++)
for (j = 0; j < PAYLOAD_ARG_CNT; j++) {
response_payload[j] = mmio_read_32(buffer_base +
(j * PAYLOAD_ARG_SIZE));
}
if (response_payload[PAYLOAD_CRC_POS] !=
calculate_crc(response_payload, IPI_W0_TO_W6_SIZE))
calculate_crc(response_payload, IPI_W0_TO_W6_SIZE)) {
NOTICE("ERROR in CRC response payload value:0x%x\n",
response_payload[PAYLOAD_CRC_POS]);
}
#endif
}
@ -226,8 +231,9 @@ enum pm_ret_status pm_ipi_send_sync(const struct pm_proc *proc,
bakery_lock_get(&pm_secure_lock);
ret = pm_ipi_send_common(proc, payload, IPI_BLOCKING);
if (ret != PM_RET_SUCCESS)
if (ret != PM_RET_SUCCESS) {
goto unlock;
}
ret = ERROR_CODE_MASK & (pm_ipi_buff_read(proc, value, count));
@ -253,10 +259,11 @@ uint32_t pm_ipi_irq_status(const struct pm_proc *proc)
ret = ipi_mb_enquire_status(proc->ipi->local_ipi_id,
proc->ipi->remote_ipi_id);
if (ret & IPI_MB_STATUS_RECV_PENDING)
if (ret & IPI_MB_STATUS_RECV_PENDING) {
return 1;
else
} else {
return 0;
}
}
#if IPI_CRC_CHECK

25
plat/xilinx/zynqmp/aarch64/zynqmp_common.c
View File

@ -47,10 +47,11 @@ unsigned int zynqmp_get_uart_clk(void)
{
unsigned int ver = zynqmp_get_silicon_ver();
if (ver == ZYNQMP_CSU_VERSION_QEMU)
if (ver == ZYNQMP_CSU_VERSION_QEMU) {
return 133000000;
else
} else {
return 100000000;
}
}
#if LOG_LEVEL >= LOG_LEVEL_NOTICE
@ -232,8 +233,9 @@ static char *zynqmp_get_silicon_idcode_name(void)
chipid[0] = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_IDCODE_OFFSET);
chipid[1] = mmio_read_32(EFUSE_BASEADDR + EFUSE_IPDISABLE_OFFSET);
#else
if (pm_get_chipid(chipid) != PM_RET_SUCCESS)
if (pm_get_chipid(chipid) != PM_RET_SUCCESS) {
return "XCZUUNKN";
}
#endif
id = chipid[0] & (ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
@ -243,8 +245,9 @@ static char *zynqmp_get_silicon_idcode_name(void)
for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
if (zynqmp_devices[i].id == id &&
zynqmp_devices[i].ver == (ver & ZYNQMP_CSU_VERSION_MASK))
zynqmp_devices[i].ver == (ver & ZYNQMP_CSU_VERSION_MASK)) {
break;
}
}
if (i >= ARRAY_SIZE(zynqmp_devices)) {
@ -255,11 +258,13 @@ static char *zynqmp_get_silicon_idcode_name(void)
}
}
if (!zynqmp_devices[i].evexists)
if (!zynqmp_devices[i].evexists) {
return zynqmp_devices[i].name;
}
if (ver & ZYNQMP_PL_STATUS_MASK)
if ((ver & ZYNQMP_PL_STATUS_MASK) != 0U) {
return zynqmp_devices[i].name;
}
len = strlen(zynqmp_devices[i].name) - 2;
for (j = 0; j < strlen(name); j++) {
@ -345,8 +350,9 @@ unsigned int zynqmp_get_bootmode(void)
ret = pm_mmio_read(CRL_APB_BOOT_MODE_USER, &r);
if (ret != PM_RET_SUCCESS)
if (ret != PM_RET_SUCCESS) {
r = mmio_read_32(CRL_APB_BOOT_MODE_USER);
}
return r & CRL_APB_BOOT_MODE_MASK;
}
@ -373,8 +379,9 @@ unsigned int plat_get_syscnt_freq2(void)
{
unsigned int ver = zynqmp_get_silicon_ver();
if (ver == ZYNQMP_CSU_VERSION_QEMU)
if (ver == ZYNQMP_CSU_VERSION_QEMU) {
return 65000000;
else
} else {
return mmio_read_32(IOU_SCNTRS_BASEFREQ);
}
}

6
plat/xilinx/zynqmp/bl31_zynqmp_setup.c
View File

@ -83,6 +83,8 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
if (rc == 0) {
panic();
}
} else {
ERROR("BL31: No console device found.\n");
}
/* Initialize the platform config for future decision making */
zynqmp_config_setup();
@ -119,10 +121,10 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
panic();
}
}
if (bl32_image_ep_info.pc) {
if (bl32_image_ep_info.pc != 0) {
VERBOSE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc);
}
if (bl33_image_ep_info.pc) {
if (bl33_image_ep_info.pc != 0) {
VERBOSE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc);
}
}

20
plat/xilinx/zynqmp/include/platform_def.h
View File

@ -37,11 +37,11 @@
*/
#ifndef ZYNQMP_ATF_MEM_BASE
#if !DEBUG && defined(SPD_none) && !SDEI_SUPPORT
# define BL31_BASE 0xfffea000
# define BL31_LIMIT 0x100000000
# define BL31_BASE U(0xfffea000)
# define BL31_LIMIT U(0x100000000)
#else
# define BL31_BASE 0x1000
# define BL31_LIMIT 0x7ffff
# define BL31_BASE U(0x1000)
# define BL31_LIMIT U(0x7ffff)
#endif
#else
# define BL31_BASE (ZYNQMP_ATF_MEM_BASE)
@ -55,8 +55,8 @@
* BL32 specific defines.
******************************************************************************/
#ifndef ZYNQMP_BL32_MEM_BASE
# define BL32_BASE 0x60000000
# define BL32_LIMIT 0x7fffffff
# define BL32_BASE U(0x60000000)
# define BL32_LIMIT U(0x7fffffff)
#else
# define BL32_BASE (ZYNQMP_BL32_MEM_BASE)
# define BL32_LIMIT (ZYNQMP_BL32_MEM_BASE + ZYNQMP_BL32_MEM_SIZE - 1)
@ -66,7 +66,7 @@
* BL33 specific defines.
******************************************************************************/
#ifndef PRELOADED_BL33_BASE
# define PLAT_ARM_NS_IMAGE_BASE 0x8000000
# define PLAT_ARM_NS_IMAGE_BASE U(0x8000000)
#else
# define PLAT_ARM_NS_IMAGE_BASE PRELOADED_BL33_BASE
#endif
@ -83,9 +83,9 @@
/*******************************************************************************
* Platform specific page table and MMU setup constants
******************************************************************************/
#define XILINX_OF_BOARD_DTB_ADDR 0x100000
#define XILINX_OF_BOARD_DTB_MAX_SIZE 0x200000
#define PLAT_DDR_LOWMEM_MAX 0x80000000
#define XILINX_OF_BOARD_DTB_ADDR U(0x100000)
#define XILINX_OF_BOARD_DTB_MAX_SIZE U(0x200000)
#define PLAT_DDR_LOWMEM_MAX U(0x80000000)
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)

30
plat/xilinx/zynqmp/include/zynqmp_def.h
View File

@ -74,11 +74,11 @@
#define ZYNQMP_ULPI_RESET_VAL_LOW CRL_APB_BOOT_ENABLE_PIN_1
/* system counter registers and bitfields */
#define IOU_SCNTRS_BASE 0xFF260000
#define IOU_SCNTRS_BASE U(0xFF260000)
#define IOU_SCNTRS_BASEFREQ (IOU_SCNTRS_BASE + 0x20)
/* APU registers and bitfields */
#define APU_BASE 0xFD5C0000
#define APU_BASE U(0xFD5C0000)
#define APU_CONFIG_0 (APU_BASE + 0x20)
#define APU_RVBAR_L_0 (APU_BASE + 0x40)
#define APU_RVBAR_H_0 (APU_BASE + 0x44)
@ -91,7 +91,7 @@
#define APU_3_PWRCTL_CPUPWRDWNREQ_MASK 8
/* PMU registers and bitfields */
#define PMU_GLOBAL_BASE 0xFFD80000
#define PMU_GLOBAL_BASE U(0xFFD80000)
#define PMU_GLOBAL_CNTRL (PMU_GLOBAL_BASE + 0)
#define PMU_GLOBAL_GEN_STORAGE6 (PMU_GLOBAL_BASE + 0x48)
#define PMU_GLOBAL_REQ_PWRUP_STATUS (PMU_GLOBAL_BASE + 0x110)
@ -104,22 +104,22 @@
/*******************************************************************************
* CCI-400 related constants
******************************************************************************/
#define PLAT_ARM_CCI_BASE 0xFD6E0000
#define PLAT_ARM_CCI_BASE U(0xFD6E0000)
#define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 3
#define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 4
/*******************************************************************************
* GIC-400 & interrupt handling related constants
******************************************************************************/
#define BASE_GICD_BASE 0xF9010000
#define BASE_GICC_BASE 0xF9020000
#define BASE_GICH_BASE 0xF9040000
#define BASE_GICV_BASE 0xF9060000
#define BASE_GICD_BASE U(0xF9010000)
#define BASE_GICC_BASE U(0xF9020000)
#define BASE_GICH_BASE U(0xF9040000)
#define BASE_GICV_BASE U(0xF9060000)
#if ZYNQMP_WDT_RESTART
#define IRQ_SEC_IPI_APU 67
#define IRQ_TTC3_1 77
#define TTC3_BASE_ADDR 0xFF140000
#define TTC3_BASE_ADDR U(0xFF140000)
#define TTC3_INTR_REGISTER_1 (TTC3_BASE_ADDR + 0x54)
#define TTC3_INTR_ENABLE_1 (TTC3_BASE_ADDR + 0x60)
#endif
@ -140,8 +140,8 @@
/*******************************************************************************
* UART related constants
******************************************************************************/
#define ZYNQMP_UART0_BASE 0xFF000000
#define ZYNQMP_UART1_BASE 0xFF010000
#define ZYNQMP_UART0_BASE U(0xFF000000)
#define ZYNQMP_UART1_BASE U(0xFF010000)
#if ZYNQMP_CONSOLE_IS(cadence) || ZYNQMP_CONSOLE_IS(dcc)
# define ZYNQMP_UART_BASE ZYNQMP_UART0_BASE
@ -169,7 +169,7 @@
#define ZYNQMP_PS_VER_MASK 0xF
#define ZYNQMP_PS_VER_SHIFT 0
#define ZYNQMP_CSU_BASEADDR 0xFFCA0000
#define ZYNQMP_CSU_BASEADDR U(0xFFCA0000)
#define ZYNQMP_CSU_IDCODE_OFFSET 0x40
#define ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT 0
@ -199,7 +199,7 @@
#define ZYNQMP_CSU_VERSION_OFFSET 0x44
/* Efuse */
#define EFUSE_BASEADDR 0xFFCC0000
#define EFUSE_BASEADDR U(0xFFCC0000)
#define EFUSE_IPDISABLE_OFFSET 0x1018
#define EFUSE_IPDISABLE_VERSION 0x1FFU
#define ZYNQMP_EFUSE_IPDISABLE_SHIFT 20
@ -357,9 +357,9 @@
#define FABRIC_WIDTH U(3)
/* CSUDMA Module Base Address*/
#define CSUDMA_BASE 0xFFC80000
#define CSUDMA_BASE U(0xFFC80000)
/* RSA-CORE Module Base Address*/
#define RSA_CORE_BASE 0xFFCE0000
#define RSA_CORE_BASE U(0xFFCE0000)
#endif /* ZYNQMP_DEF_H */

28
plat/xilinx/zynqmp/plat_psci.c
View File

@ -38,9 +38,9 @@ static int zynqmp_pwr_domain_on(u_register_t mpidr)
VERBOSE("%s: mpidr: 0x%lx\n", __func__, mpidr);
if (cpu_id == -1)
if (cpu_id == -1) {
return PSCI_E_INTERN_FAIL;
}
proc = pm_get_proc(cpu_id);
/* Check the APU proc status before wakeup */
@ -63,9 +63,10 @@ static void zynqmp_pwr_domain_off(const psci_power_state_t *target_state)
unsigned int cpu_id = plat_my_core_pos();
const struct pm_proc *proc = pm_get_proc(cpu_id);
for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) {
VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
__func__, i, target_state->pwr_domain_state[i]);
}
/* Prevent interrupts from spuriously waking up this cpu */
gicv2_cpuif_disable();
@ -106,9 +107,10 @@ static void zynqmp_pwr_domain_suspend(const psci_power_state_t *target_state)
static void zynqmp_pwr_domain_on_finish(const psci_power_state_t *target_state)
{
for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) {
VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
__func__, i, target_state->pwr_domain_state[i]);
}
plat_arm_gic_pcpu_init();
gicv2_cpuif_enable();
}
@ -118,9 +120,10 @@ static void zynqmp_pwr_domain_suspend_finish(const psci_power_state_t *target_st
unsigned int cpu_id = plat_my_core_pos();
const struct pm_proc *proc = pm_get_proc(cpu_id);
for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) {
VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
__func__, i, target_state->pwr_domain_state[i]);
}
/* Clear the APU power control register for this cpu */
pm_client_wakeup(proc);
@ -149,8 +152,9 @@ static void __dead2 zynqmp_system_off(void)
pm_system_shutdown(PMF_SHUTDOWN_TYPE_SHUTDOWN,
pm_get_shutdown_scope());
while (1)
while (1) {
wfi();
}
}
static void __dead2 zynqmp_system_reset(void)
@ -162,8 +166,9 @@ static void __dead2 zynqmp_system_reset(void)
pm_system_shutdown(PMF_SHUTDOWN_TYPE_RESET,
pm_get_shutdown_scope());
while (1)
while (1) {
wfi();
}
}
int zynqmp_validate_power_state(unsigned int power_state,
@ -176,14 +181,15 @@ int zynqmp_validate_power_state(unsigned int power_state,
assert(req_state);
/* Sanity check the requested state */
if (pstate == PSTATE_TYPE_STANDBY)
if (pstate == PSTATE_TYPE_STANDBY) {
req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE;
else
} else {
req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE;
}
/* We expect the 'state id' to be zero */
if (psci_get_pstate_id(power_state))
if (psci_get_pstate_id(power_state)) {
return PSCI_E_INVALID_PARAMS;
}
return PSCI_E_SUCCESS;
}

120
plat/xilinx/zynqmp/pm_service/pm_api_clock.c
View File

@ -2446,16 +2446,17 @@ enum pm_ret_status pm_api_clock_get_num_clocks(unsigned int *nclocks)
*/
void pm_api_clock_get_name(unsigned int clock_id, char *name)
{
if (clock_id == CLK_MAX)
if (clock_id == CLK_MAX) {
memcpy(name, END_OF_CLK, sizeof(END_OF_CLK) > CLK_NAME_LEN ?
CLK_NAME_LEN : sizeof(END_OF_CLK));
else if (!pm_clock_valid(clock_id))
} else if (!pm_clock_valid(clock_id)) {
memset(name, 0, CLK_NAME_LEN);
else if (clock_id < CLK_MAX_OUTPUT_CLK)
} else if (clock_id < CLK_MAX_OUTPUT_CLK) {
memcpy(name, clocks[clock_id].name, CLK_NAME_LEN);
else
} else {
memcpy(name, ext_clocks[clock_id - CLK_MAX_OUTPUT_CLK].name,
CLK_NAME_LEN);
}
}
/**
@ -2480,24 +2481,28 @@ enum pm_ret_status pm_api_clock_get_topology(unsigned int clock_id,
unsigned int i;
uint16_t typeflags;
if (!pm_clock_valid(clock_id))
if (!pm_clock_valid(clock_id)) {
return PM_RET_ERROR_ARGS;
}
if (pm_clock_type(clock_id) != CLK_TYPE_OUTPUT)
if (pm_clock_type(clock_id) != CLK_TYPE_OUTPUT) {
return PM_RET_ERROR_NOTSUPPORTED;
}
memset(topology, 0, CLK_TOPOLOGY_PAYLOAD_LEN);
clock_nodes = *clocks[clock_id].nodes;
num_nodes = clocks[clock_id].num_nodes;
/* Skip parent till index */
if (index >= num_nodes)
if (index >= num_nodes) {
return PM_RET_SUCCESS;
}
for (i = 0; i < 3U; i++) {
if ((index + i) == num_nodes)
if ((index + i) == num_nodes) {
break;
}
topology[i] = clock_nodes[index + i].type;
topology[i] |= clock_nodes[index + i].clkflags <<
CLK_CLKFLAGS_SHIFT;
@ -2531,11 +2536,13 @@ enum pm_ret_status pm_api_clock_get_fixedfactor_params(unsigned int clock_id,
uint8_t num_nodes;
unsigned int type, i;
if (!pm_clock_valid(clock_id))
if (!pm_clock_valid(clock_id)) {
return PM_RET_ERROR_ARGS;
}
if (pm_clock_type(clock_id) != CLK_TYPE_OUTPUT)
if (pm_clock_type(clock_id) != CLK_TYPE_OUTPUT) {
return PM_RET_ERROR_NOTSUPPORTED;
}
clock_nodes = *clocks[clock_id].nodes;
num_nodes = clocks[clock_id].num_nodes;
@ -2550,8 +2557,9 @@ enum pm_ret_status pm_api_clock_get_fixedfactor_params(unsigned int clock_id,
}
/* Clock is not fixed clock */
if (i == num_nodes)
if (i == num_nodes) {
return PM_RET_ERROR_ARGS;
}
return PM_RET_SUCCESS;
}
@ -2580,27 +2588,33 @@ enum pm_ret_status pm_api_clock_get_parents(unsigned int clock_id,
unsigned int i;
int32_t *clk_parents;
if (!pm_clock_valid(clock_id))
if (!pm_clock_valid(clock_id)) {
return PM_RET_ERROR_ARGS;
}
if (pm_clock_type(clock_id) != CLK_TYPE_OUTPUT)
if (pm_clock_type(clock_id) != CLK_TYPE_OUTPUT) {
return PM_RET_ERROR_NOTSUPPORTED;
}
clk_parents = *clocks[clock_id].parents;
if (clk_parents == NULL)
if (clk_parents == NULL) {
return PM_RET_ERROR_ARGS;
}
memset(parents, 0, CLK_PARENTS_PAYLOAD_LEN);
/* Skip parent till index */
for (i = 0; i < index; i++)
if (clk_parents[i] == CLK_NA_PARENT)
for (i = 0; i < index; i++) {
if (clk_parents[i] == CLK_NA_PARENT) {
return PM_RET_SUCCESS;
}
}
for (i = 0; i < 3; i++) {
parents[i] = clk_parents[index + i];
if (clk_parents[index + i] == CLK_NA_PARENT)
if (clk_parents[index + i] == CLK_NA_PARENT) {
break;
}
}
return PM_RET_SUCCESS;
@ -2619,8 +2633,9 @@ enum pm_ret_status pm_api_clock_get_parents(unsigned int clock_id,
enum pm_ret_status pm_api_clock_get_attributes(unsigned int clock_id,
uint32_t *attr)
{
if (clock_id >= CLK_MAX)
if (clock_id >= CLK_MAX) {
return PM_RET_ERROR_ARGS;
}
/* Clock valid bit */
*attr = pm_clock_valid(clock_id);
@ -2648,8 +2663,9 @@ enum pm_ret_status pm_api_clock_get_max_divisor(enum clock_id clock_id,
uint32_t i;
struct pm_clock_node *nodes;
if (clock_id >= CLK_MAX_OUTPUT_CLK)
if (clock_id >= CLK_MAX_OUTPUT_CLK) {
return PM_RET_ERROR_ARGS;
}
nodes = *clocks[clock_id].nodes;
for (i = 0; i < clocks[clock_id].num_nodes; i++) {
@ -2738,8 +2754,9 @@ struct pm_pll *pm_clock_get_pll(enum clock_id clock_id)
uint32_t i;
for (i = 0; i < ARRAY_SIZE(pm_plls); i++) {
if (pm_plls[i].cid == clock_id)
if (pm_plls[i].cid == clock_id) {
return &pm_plls[i];
}
}
return NULL;
@ -2798,12 +2815,14 @@ struct pm_pll *pm_clock_get_pll_by_related_clk(enum clock_id clock_id)
*/
enum pm_ret_status pm_clock_pll_enable(struct pm_pll *pll)
{
if (!pll)
if (!pll) {
return PM_RET_ERROR_ARGS;
}
/* Set the PLL mode according to the buffered mode value */
if (pll->mode == PLL_FRAC_MODE)
if (pll->mode == PLL_FRAC_MODE) {
return pm_pll_set_mode(pll->nid, PM_PLL_MODE_FRACTIONAL);
}
return pm_pll_set_mode(pll->nid, PM_PLL_MODE_INTEGER);
}
@ -2819,8 +2838,9 @@ enum pm_ret_status pm_clock_pll_enable(struct pm_pll *pll)
*/
enum pm_ret_status pm_clock_pll_disable(struct pm_pll *pll)
{
if (!pll)
if (!pll) {
return PM_RET_ERROR_ARGS;
}
return pm_pll_set_mode(pll->nid, PM_PLL_MODE_RESET);
}
@ -2842,17 +2862,20 @@ enum pm_ret_status pm_clock_pll_get_state(struct pm_pll *pll,
enum pm_ret_status status;
enum pm_pll_mode mode;
if (!pll || !state)
if (!pll || !state) {
return PM_RET_ERROR_ARGS;
}
status = pm_pll_get_mode(pll->nid, &mode);
if (status != PM_RET_SUCCESS)
if (status != PM_RET_SUCCESS) {
return status;
}
if (mode == PM_PLL_MODE_RESET)
if (mode == PM_PLL_MODE_RESET) {
*state = 0;
else
} else {
*state = 1;
}
return PM_RET_SUCCESS;
}
@ -2873,17 +2896,21 @@ enum pm_ret_status pm_clock_pll_set_parent(struct pm_pll *pll,
enum clock_id clock_id,
unsigned int parent_index)
{
if (!pll)
if (!pll) {
return PM_RET_ERROR_ARGS;
if (pll->pre_src == clock_id)
}
if (pll->pre_src == clock_id) {
return pm_pll_set_parameter(pll->nid, PM_PLL_PARAM_PRE_SRC,
parent_index);
if (pll->post_src == clock_id)
}
if (pll->post_src == clock_id) {
return pm_pll_set_parameter(pll->nid, PM_PLL_PARAM_POST_SRC,
parent_index);
if (pll->div2 == clock_id)
}
if (pll->div2 == clock_id) {
return pm_pll_set_parameter(pll->nid, PM_PLL_PARAM_DIV2,
parent_index);
}
return PM_RET_ERROR_ARGS;
}
@ -2902,17 +2929,21 @@ enum pm_ret_status pm_clock_pll_get_parent(struct pm_pll *pll,
enum clock_id clock_id,
unsigned int *parent_index)
{
if (!pll)
if (!pll) {
return PM_RET_ERROR_ARGS;
if (pll->pre_src == clock_id)
}
if (pll->pre_src == clock_id) {
return pm_pll_get_parameter(pll->nid, PM_PLL_PARAM_PRE_SRC,
parent_index);
if (pll->post_src == clock_id)
}
if (pll->post_src == clock_id) {
return pm_pll_get_parameter(pll->nid, PM_PLL_PARAM_POST_SRC,
parent_index);
if (pll->div2 == clock_id)
}
if (pll->div2 == clock_id) {
return pm_pll_get_parameter(pll->nid, PM_PLL_PARAM_DIV2,
parent_index);
}
if (pll->bypass == clock_id) {
*parent_index = 0;
return PM_RET_SUCCESS;
@ -2935,8 +2966,9 @@ enum pm_ret_status pm_clock_set_pll_mode(enum clock_id clock_id,
{
struct pm_pll *pll = pm_clock_get_pll(clock_id);
if (!pll || (mode != PLL_FRAC_MODE && mode != PLL_INT_MODE))
if (!pll || (mode != PLL_FRAC_MODE && mode != PLL_INT_MODE)) {
return PM_RET_ERROR_ARGS;
}
pll->mode = mode;
return PM_RET_SUCCESS;
@ -2956,8 +2988,9 @@ enum pm_ret_status pm_clock_get_pll_mode(enum clock_id clock_id,
{
struct pm_pll *pll = pm_clock_get_pll(clock_id);
if (!pll || !mode)
if (!pll || !mode) {
return PM_RET_ERROR_ARGS;
}
*mode = pll->mode;
return PM_RET_SUCCESS;
@ -2971,11 +3004,13 @@ enum pm_ret_status pm_clock_get_pll_mode(enum clock_id clock_id,
*/
enum pm_ret_status pm_clock_id_is_valid(unsigned int clock_id)
{
if (!pm_clock_valid(clock_id))
if (!pm_clock_valid(clock_id)) {
return PM_RET_ERROR_ARGS;
}
if (pm_clock_type(clock_id) != CLK_TYPE_OUTPUT)
if (pm_clock_type(clock_id) != CLK_TYPE_OUTPUT) {
return PM_RET_ERROR_NOTSUPPORTED;
}
return PM_RET_SUCCESS;
}
@ -2992,8 +3027,9 @@ uint8_t pm_clock_has_div(unsigned int clock_id, enum pm_clock_div_id div_id)
uint32_t i;
struct pm_clock_node *nodes;
if (clock_id >= CLK_MAX_OUTPUT_CLK)
if (clock_id >= CLK_MAX_OUTPUT_CLK) {
return 0;
}
nodes = *clocks[clock_id].nodes;
for (i = 0; i < clocks[clock_id].num_nodes; i++) {
@ -3003,6 +3039,8 @@ uint8_t pm_clock_has_div(unsigned int clock_id, enum pm_clock_div_id div_id)
} else if (nodes[i].type == TYPE_DIV2) {
if (div_id == PM_CLOCK_DIV1_ID)
return 1;
} else {
/* To fix the misra 15.7 warning */
}
}

133
plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c
View File

@ -35,10 +35,11 @@ static enum pm_ret_status pm_ioctl_get_rpu_oper_mode(unsigned int *mode)
val = mmio_read_32(ZYNQMP_RPU_GLBL_CNTL);
val &= ZYNQMP_SLSPLIT_MASK;
if (val == 0)
if (val == 0) {
*mode = PM_RPU_MODE_LOCKSTEP;
else
} else {
*mode = PM_RPU_MODE_SPLIT;
}
return PM_RET_SUCCESS;
}
@ -58,8 +59,9 @@ static enum pm_ret_status pm_ioctl_set_rpu_oper_mode(unsigned int mode)
{
unsigned int val;
if (mmio_read_32(CRL_APB_RST_LPD_TOP) & CRL_APB_RPU_AMBA_RESET)
if (mmio_read_32(CRL_APB_RST_LPD_TOP) & CRL_APB_RPU_AMBA_RESET) {
return PM_RET_ERROR_ACCESS;
}
val = mmio_read_32(ZYNQMP_RPU_GLBL_CNTL);
@ -94,21 +96,23 @@ static enum pm_ret_status pm_ioctl_config_boot_addr(enum pm_node_id nid,
{
unsigned int rpu_cfg_addr, val;
if (nid == NODE_RPU_0)
if (nid == NODE_RPU_0) {
rpu_cfg_addr = ZYNQMP_RPU0_CFG;
else if (nid == NODE_RPU_1)
} else if (nid == NODE_RPU_1) {
rpu_cfg_addr = ZYNQMP_RPU1_CFG;
else
} else {
return PM_RET_ERROR_ARGS;
}
val = mmio_read_32(rpu_cfg_addr);
if (value == PM_RPU_BOOTMEM_LOVEC)
if (value == PM_RPU_BOOTMEM_LOVEC) {
val &= ~ZYNQMP_VINITHI_MASK;
else if (value == PM_RPU_BOOTMEM_HIVEC)
} else if (value == PM_RPU_BOOTMEM_HIVEC) {
val |= ZYNQMP_VINITHI_MASK;
else
} else {
return PM_RET_ERROR_ARGS;
}
mmio_write_32(rpu_cfg_addr, val);
@ -130,12 +134,13 @@ static enum pm_ret_status pm_ioctl_config_tcm_comb(unsigned int value)
val = mmio_read_32(ZYNQMP_RPU_GLBL_CNTL);
if (value == PM_RPU_TCM_SPLIT)
if (value == PM_RPU_TCM_SPLIT) {
val &= ~ZYNQMP_TCM_COMB_MASK;
else if (value == PM_RPU_TCM_COMB)
} else if (value == PM_RPU_TCM_COMB) {
val |= ZYNQMP_TCM_COMB_MASK;
else
} else {
return PM_RET_ERROR_ARGS;
}
mmio_write_32(ZYNQMP_RPU_GLBL_CNTL, val);
@ -155,8 +160,9 @@ static enum pm_ret_status pm_ioctl_set_tapdelay_bypass(unsigned int type,
unsigned int value)
{
if ((value != PM_TAPDELAY_BYPASS_ENABLE &&
value != PM_TAPDELAY_BYPASS_DISABLE) || type >= PM_TAPDELAY_MAX)
value != PM_TAPDELAY_BYPASS_DISABLE) || type >= PM_TAPDELAY_MAX) {
return PM_RET_ERROR_ARGS;
}
return pm_mmio_write(IOU_TAPDLY_BYPASS, TAP_DELAY_MASK, value << type);
}
@ -178,8 +184,9 @@ static enum pm_ret_status pm_ioctl_set_sgmii_mode(enum pm_node_id nid,
unsigned int val, mask, shift;
enum pm_ret_status ret;
if (value != PM_SGMII_DISABLE && value != PM_SGMII_ENABLE)
if (value != PM_SGMII_DISABLE && value != PM_SGMII_ENABLE) {
return PM_RET_ERROR_ARGS;
}
switch (nid) {
case NODE_ETH_0:
@ -206,8 +213,9 @@ static enum pm_ret_status pm_ioctl_set_sgmii_mode(enum pm_node_id nid,
mask = SGMII_SD_MASK << SGMII_SD_OFFSET * shift;
val = SGMII_PCS_SD_1 << SGMII_SD_OFFSET * shift;
ret = pm_mmio_write(IOU_GEM_CTRL, mask, val);
if (ret != PM_RET_SUCCESS)
if (ret != PM_RET_SUCCESS) {
return ret;
}
/* Set the GEM to SGMII mode */
mask = GEM_CLK_CTRL_MASK << GEM_CLK_CTRL_OFFSET * shift;
@ -248,11 +256,13 @@ static enum pm_ret_status pm_ioctl_sd_dll_reset(enum pm_node_id nid,
case PM_DLL_RESET_ASSERT:
case PM_DLL_RESET_PULSE:
ret = pm_mmio_write(ZYNQMP_SD_DLL_CTRL, mask, val);
if (ret != PM_RET_SUCCESS)
if (ret != PM_RET_SUCCESS) {
return ret;
}
if (type == PM_DLL_RESET_ASSERT)
if (type == PM_DLL_RESET_ASSERT) {
break;
}
mdelay(1);
/* Fallthrough */
case PM_DLL_RESET_RELEASE:
@ -310,31 +320,44 @@ static enum pm_ret_status pm_ioctl_sd_set_tapdelay(enum pm_node_id nid,
ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
(ZYNQMP_SD_ITAPCHGWIN_MASK << shift),
(ZYNQMP_SD_ITAPCHGWIN << shift));
if (ret != PM_RET_SUCCESS)
if (ret != PM_RET_SUCCESS) {
goto reset_release;
if (value == 0)
}
if (value == 0) {
ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
(ZYNQMP_SD_ITAPDLYENA_MASK <<
shift), 0);
else
} else {
ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
(ZYNQMP_SD_ITAPDLYENA_MASK <<
shift), (ZYNQMP_SD_ITAPDLYENA <<
shift));
if (ret != PM_RET_SUCCESS)
}
if (ret != PM_RET_SUCCESS) {
goto reset_release;
}
ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
(ZYNQMP_SD_ITAPDLYSEL_MASK << shift),
(value << shift));
if (ret != PM_RET_SUCCESS)
if (ret != PM_RET_SUCCESS) {
goto reset_release;
}
ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
(ZYNQMP_SD_ITAPCHGWIN_MASK << shift), 0);
} else if (type == PM_TAPDELAY_OUTPUT) {
ret = pm_mmio_write(ZYNQMP_SD_OTAP_DLY,
(ZYNQMP_SD_OTAPDLYENA_MASK << shift), 0);
if (ret != PM_RET_SUCCESS)
if (ret != PM_RET_SUCCESS) {
goto reset_release;
}
ret = pm_mmio_write(ZYNQMP_SD_OTAP_DLY,
(ZYNQMP_SD_OTAPDLYSEL_MASK << shift),
(value << shift));
@ -401,8 +424,9 @@ static enum pm_ret_status pm_ioctl_set_pll_frac_data
/* Get PLL node ID using PLL clock ID */
status = pm_clock_get_pll_node_id(pll, &pll_nid);
if (status != PM_RET_SUCCESS)
if (status != PM_RET_SUCCESS) {
return status;
}
return pm_pll_set_parameter(pll_nid, PM_PLL_PARAM_DATA, data);
}
@ -425,8 +449,9 @@ static enum pm_ret_status pm_ioctl_get_pll_frac_data
/* Get PLL node ID using PLL clock ID */
status = pm_clock_get_pll_node_id(pll, &pll_nid);
if (status != PM_RET_SUCCESS)
if (status != PM_RET_SUCCESS) {
return status;
}
return pm_pll_get_parameter(pll_nid, PM_PLL_PARAM_DATA, data);
}
@ -444,8 +469,9 @@ static enum pm_ret_status pm_ioctl_get_pll_frac_data
static enum pm_ret_status pm_ioctl_write_ggs(unsigned int index,
unsigned int value)
{
if (index >= GGS_NUM_REGS)
if (index >= GGS_NUM_REGS) {
return PM_RET_ERROR_ARGS;
}
return pm_mmio_write(GGS_BASEADDR + (index << 2),
0xFFFFFFFFU, value);
@ -464,8 +490,9 @@ static enum pm_ret_status pm_ioctl_write_ggs(unsigned int index,
static enum pm_ret_status pm_ioctl_read_ggs(unsigned int index,
unsigned int *value)
{
if (index >= GGS_NUM_REGS)
if (index >= GGS_NUM_REGS) {
return PM_RET_ERROR_ARGS;
}
return pm_mmio_read(GGS_BASEADDR + (index << 2), value);
}
@ -483,8 +510,9 @@ static enum pm_ret_status pm_ioctl_read_ggs(unsigned int index,
static enum pm_ret_status pm_ioctl_write_pggs(unsigned int index,
unsigned int value)
{
if (index >= PGGS_NUM_REGS)
if (index >= PGGS_NUM_REGS) {
return PM_RET_ERROR_ARGS;
}
return pm_mmio_write(PGGS_BASEADDR + (index << 2),
0xFFFFFFFFU, value);
@ -503,31 +531,33 @@ static enum pm_ret_status pm_ioctl_afi(unsigned int index,
unsigned int value)
{
unsigned int mask;
unsigned int regarr[] = {0xFD360000,
0xFD360014,
0xFD370000,
0xFD370014,
0xFD380000,
0xFD380014,
0xFD390000,
0xFD390014,
0xFD3a0000,
0xFD3a0014,
0xFD3b0000,
0xFD3b0014,
0xFF9b0000,
0xFF9b0014,
0xFD615000,
0xFF419000,
unsigned int regarr[] = {0xFD360000U,
0xFD360014U,
0xFD370000U,
0xFD370014U,
0xFD380000U,
0xFD380014U,
0xFD390000U,
0xFD390014U,
0xFD3a0000U,
0xFD3a0014U,
0xFD3b0000U,
0xFD3b0014U,
0xFF9b0000U,
0xFF9b0014U,
0xFD615000U,
0xFF419000U,
};
if (index >= ARRAY_SIZE(regarr))
if (index >= ARRAY_SIZE(regarr)) {
return PM_RET_ERROR_ARGS;
}
if (index < AFIFM6_WRCTRL)
if (index < AFIFM6_WRCTRL) {
mask = FABRIC_WIDTH;
else
} else {
mask = 0xf00;
}
return pm_mmio_write(regarr[index], mask, value);
}
@ -545,8 +575,9 @@ static enum pm_ret_status pm_ioctl_afi(unsigned int index,
static enum pm_ret_status pm_ioctl_read_pggs(unsigned int index,
unsigned int *value)
{
if (index >= PGGS_NUM_REGS)
if (index >= PGGS_NUM_REGS) {
return PM_RET_ERROR_ARGS;
}
return pm_mmio_read(PGGS_BASEADDR + (index << 2), value);
}
@ -565,16 +596,18 @@ static enum pm_ret_status pm_ioctl_ulpi_reset(void)
ret = pm_mmio_write(CRL_APB_BOOT_PIN_CTRL, CRL_APB_BOOT_PIN_MASK,
ZYNQMP_ULPI_RESET_VAL_HIGH);
if (ret != PM_RET_SUCCESS)
if (ret != PM_RET_SUCCESS) {
return ret;
}
/* Drive ULPI assert for atleast 1ms */
mdelay(1);
ret = pm_mmio_write(CRL_APB_BOOT_PIN_CTRL, CRL_APB_BOOT_PIN_MASK,
ZYNQMP_ULPI_RESET_VAL_LOW);
if (ret != PM_RET_SUCCESS)
if (ret != PM_RET_SUCCESS) {
return ret;
}
/* Drive ULPI de-assert for atleast 1ms */
mdelay(1);

44
plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c
View File

@ -2549,17 +2549,20 @@ enum pm_ret_status pm_api_pinctrl_get_num_func_groups(unsigned int fid,
int i = 0;
uint16_t *grps;
if (fid >= MAX_FUNCTION)
if (fid >= MAX_FUNCTION) {
return PM_RET_ERROR_ARGS;
}
*ngroups = 0;
grps = *pinctrl_functions[fid].groups;
if (grps == NULL)
if (grps == NULL) {
return PM_RET_SUCCESS;
}
while (grps[i++] != (uint16_t)END_OF_GROUPS)
while (grps[i++] != (uint16_t)END_OF_GROUPS) {
(*ngroups)++;
}
return PM_RET_SUCCESS;
}
@ -2574,10 +2577,11 @@ enum pm_ret_status pm_api_pinctrl_get_num_func_groups(unsigned int fid,
*/
void pm_api_pinctrl_get_function_name(unsigned int fid, char *name)
{
if (fid >= MAX_FUNCTION)
if (fid >= MAX_FUNCTION) {
memcpy(name, END_OF_FUNCTION, FUNCTION_NAME_LEN);
else
} else {
memcpy(name, pinctrl_functions[fid].name, FUNCTION_NAME_LEN);
}
}
/**
@ -2605,24 +2609,29 @@ enum pm_ret_status pm_api_pinctrl_get_function_groups(unsigned int fid,
unsigned int i;
uint16_t *grps;
if (fid >= MAX_FUNCTION)
if (fid >= MAX_FUNCTION) {
return PM_RET_ERROR_ARGS;
}
memset(groups, END_OF_GROUPS, GROUPS_PAYLOAD_LEN);
grps = *pinctrl_functions[fid].groups;
if (grps == NULL)
if (grps == NULL) {
return PM_RET_SUCCESS;
}
/* Skip groups till index */
for (i = 0; i < index; i++)
if (grps[i] == (uint16_t)END_OF_GROUPS)
for (i = 0; i < index; i++) {
if (grps[i] == (uint16_t)END_OF_GROUPS) {
return PM_RET_SUCCESS;
}
}
for (i = 0; i < NUM_GROUPS_PER_RESP; i++) {
groups[i] = grps[index + i];
if (groups[i] == (uint16_t)END_OF_GROUPS)
if (groups[i] == (uint16_t)END_OF_GROUPS) {
break;
}
}
return PM_RET_SUCCESS;
@ -2653,24 +2662,29 @@ enum pm_ret_status pm_api_pinctrl_get_pin_groups(unsigned int pin,
unsigned int i;
uint16_t *grps;
if (pin >= MAX_PIN)
if (pin >= MAX_PIN) {
return PM_RET_ERROR_ARGS;
}
memset(groups, END_OF_GROUPS, GROUPS_PAYLOAD_LEN);
grps = *zynqmp_pin_groups[pin].groups;
if (!grps)
if (grps == NULL) {
return PM_RET_SUCCESS;
}
/* Skip groups till index */
for (i = 0; i < index; i++)
if (grps[i] == (uint16_t)END_OF_GROUPS)
for (i = 0; i < index; i++) {
if (grps[i] == (uint16_t)END_OF_GROUPS) {
return PM_RET_SUCCESS;
}
}
for (i = 0; i < NUM_GROUPS_PER_RESP; i++) {
groups[i] = grps[index + i];
if (groups[i] == (uint16_t)END_OF_GROUPS)
if (groups[i] == (uint16_t)END_OF_GROUPS) {
break;
}
}
return PM_RET_SUCCESS;

104
plat/xilinx/zynqmp/pm_service/pm_api_sys.c
View File

@ -306,10 +306,11 @@ enum pm_ret_status pm_req_suspend(enum pm_node_id target,
/* Send request to the PMU */
PM_PACK_PAYLOAD5(payload, PM_REQ_SUSPEND, target, ack, latency, state);
if (ack == REQ_ACK_BLOCKING)
if (ack == REQ_ACK_BLOCKING) {
return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
else
} else {
return pm_ipi_send(primary_proc, payload);
}
}
/**
@ -345,10 +346,11 @@ enum pm_ret_status pm_req_wakeup(enum pm_node_id target,
PM_PACK_PAYLOAD5(payload, PM_REQ_WAKEUP, target, encoded_address,
encoded_address >> 32, ack);
if (ack == REQ_ACK_BLOCKING)
if (ack == REQ_ACK_BLOCKING) {
return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
else
} else {
return pm_ipi_send(primary_proc, payload);
}
}
/**
@ -367,10 +369,11 @@ enum pm_ret_status pm_force_powerdown(enum pm_node_id target,
/* Send request to the PMU */
PM_PACK_PAYLOAD3(payload, PM_FORCE_POWERDOWN, target, ack);
if (ack == REQ_ACK_BLOCKING)
if (ack == REQ_ACK_BLOCKING) {
return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
else
} else {
return pm_ipi_send(primary_proc, payload);
}
}
/**
@ -459,10 +462,11 @@ enum pm_ret_status pm_req_node(enum pm_node_id nid,
PM_PACK_PAYLOAD5(payload, PM_REQ_NODE, nid, capabilities, qos, ack);
if (ack == REQ_ACK_BLOCKING)
if (ack == REQ_ACK_BLOCKING) {
return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
else
} else {
return pm_ipi_send(primary_proc, payload);
}
}
/**
@ -486,10 +490,11 @@ enum pm_ret_status pm_set_requirement(enum pm_node_id nid,
PM_PACK_PAYLOAD5(payload, PM_SET_REQUIREMENT, nid, capabilities, qos,
ack);
if (ack == REQ_ACK_BLOCKING)
if (ack == REQ_ACK_BLOCKING) {
return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
else
} else {
return pm_ipi_send(primary_proc, payload);
}
}
/* Miscellaneous API functions */
@ -689,8 +694,9 @@ enum pm_ret_status pm_aes_engine(uint32_t address_high,
void pm_get_callbackdata(uint32_t *data, size_t count)
{
/* Return if interrupt is not from PMU */
if (!pm_ipi_irq_status(primary_proc))
if (!pm_ipi_irq_status(primary_proc)) {
return;
}
pm_ipi_buff_read_callb(data, count);
pm_ipi_irq_clear(primary_proc);
@ -1070,21 +1076,24 @@ static enum pm_ret_status pm_clock_gate(unsigned int clock_id,
/* Check if clock ID is valid and return an error if it is not */
status = pm_clock_id_is_valid(clock_id);
if (status != PM_RET_SUCCESS)
if (status != PM_RET_SUCCESS) {
return status;
}
if (enable)
if (enable) {
api_id = PM_CLOCK_ENABLE;
else
} else {
api_id = PM_CLOCK_DISABLE;
}
/* Send request to the PMU */
PM_PACK_PAYLOAD2(payload, api_id, clock_id);
status = pm_ipi_send_sync(primary_proc, payload, NULL, 0);
/* If action fails due to the lack of permissions filter the error */
if (status == PM_RET_ERROR_ACCESS)
if (status == PM_RET_ERROR_ACCESS) {
status = PM_RET_SUCCESS;
}
return status;
}
@ -1105,8 +1114,9 @@ enum pm_ret_status pm_clock_enable(unsigned int clock_id)
/* First try to handle it as a PLL */
pll = pm_clock_get_pll(clock_id);
if (pll)
if (pll) {
return pm_clock_pll_enable(pll);
}
/* It's an on-chip clock, PMU should configure clock's gate */
return pm_clock_gate(clock_id, 1);
@ -1128,8 +1138,9 @@ enum pm_ret_status pm_clock_disable(unsigned int clock_id)
/* First try to handle it as a PLL */
pll = pm_clock_get_pll(clock_id);
if (pll)
if (pll) {
return pm_clock_pll_disable(pll);
}
/* It's an on-chip clock, PMU should configure clock's gate */
return pm_clock_gate(clock_id, 0);
@ -1159,8 +1170,9 @@ enum pm_ret_status pm_clock_getstate(unsigned int clock_id,
/* Check if clock ID is a valid on-chip clock */
status = pm_clock_id_is_valid(clock_id);
if (status != PM_RET_SUCCESS)
if (status != PM_RET_SUCCESS) {
return status;
}
/* Send request to the PMU */
PM_PACK_PAYLOAD2(payload, PM_CLOCK_GETSTATE, clock_id);
@ -1190,13 +1202,15 @@ enum pm_ret_status pm_clock_setdivider(unsigned int clock_id,
/* Get PLL node ID using PLL clock ID */
status = pm_clock_get_pll_node_id(clock_id, &nid);
if (status == PM_RET_SUCCESS)
if (status == PM_RET_SUCCESS) {
return pm_pll_set_parameter(nid, PM_PLL_PARAM_FBDIV, divider);
}
/* Check if clock ID is a valid on-chip clock */
status = pm_clock_id_is_valid(clock_id);
if (status != PM_RET_SUCCESS)
if (status != PM_RET_SUCCESS) {
return status;
}
if (div0 == (divider & div0)) {
div_id = PM_CLOCK_DIV0_ID;
@ -1233,21 +1247,24 @@ enum pm_ret_status pm_clock_getdivider(unsigned int clock_id,
/* Get PLL node ID using PLL clock ID */
status = pm_clock_get_pll_node_id(clock_id, &nid);
if (status == PM_RET_SUCCESS)
if (status == PM_RET_SUCCESS) {
return pm_pll_get_parameter(nid, PM_PLL_PARAM_FBDIV, divider);
}
/* Check if clock ID is a valid on-chip clock */
status = pm_clock_id_is_valid(clock_id);
if (status != PM_RET_SUCCESS)
if (status != PM_RET_SUCCESS) {
return status;
}
if (pm_clock_has_div(clock_id, PM_CLOCK_DIV0_ID)) {
/* Send request to the PMU to get div0 */
PM_PACK_PAYLOAD3(payload, PM_CLOCK_GETDIVIDER, clock_id,
PM_CLOCK_DIV0_ID);
status = pm_ipi_send_sync(primary_proc, payload, &val, 1);
if (status != PM_RET_SUCCESS)
if (status != PM_RET_SUCCESS) {
return status;
}
*divider = val;
}
@ -1256,8 +1273,9 @@ enum pm_ret_status pm_clock_getdivider(unsigned int clock_id,
PM_PACK_PAYLOAD3(payload, PM_CLOCK_GETDIVIDER, clock_id,
PM_CLOCK_DIV1_ID);
status = pm_ipi_send_sync(primary_proc, payload, &val, 1);
if (status != PM_RET_SUCCESS)
if (status != PM_RET_SUCCESS) {
return status;
}
*divider |= val << 16;
}
@ -1313,13 +1331,15 @@ enum pm_ret_status pm_clock_setparent(unsigned int clock_id,
/* First try to handle it as a PLL */
pll = pm_clock_get_pll_by_related_clk(clock_id);
if (pll)
if (pll) {
return pm_clock_pll_set_parent(pll, clock_id, parent_index);
}
/* Check if clock ID is a valid on-chip clock */
status = pm_clock_id_is_valid(clock_id);
if (status != PM_RET_SUCCESS)
if (status != PM_RET_SUCCESS) {
return status;
}
/* Send request to the PMU */
PM_PACK_PAYLOAD3(payload, PM_CLOCK_SETPARENT, clock_id, parent_index);
@ -1345,13 +1365,15 @@ enum pm_ret_status pm_clock_getparent(unsigned int clock_id,
/* First try to handle it as a PLL */
pll = pm_clock_get_pll_by_related_clk(clock_id);
if (pll)
if (pll) {
return pm_clock_pll_get_parent(pll, clock_id, parent_index);
}
/* Check if clock ID is a valid on-chip clock */
status = pm_clock_id_is_valid(clock_id);
if (status != PM_RET_SUCCESS)
if (status != PM_RET_SUCCESS) {
return status;
}
/* Send request to the PMU */
PM_PACK_PAYLOAD2(payload, PM_CLOCK_GETPARENT, clock_id);
@ -1522,6 +1544,7 @@ void pm_query_data(enum pm_query_id qid, unsigned int arg1, unsigned int arg2,
default:
data[0] = PM_RET_ERROR_ARGS;
WARN("Unimplemented query service call: 0x%x\n", qid);
break;
}
}
@ -1614,12 +1637,14 @@ enum pm_ret_status pm_pll_set_parameter(enum pm_node_id nid,
uint32_t payload[PAYLOAD_ARG_CNT];
/* Check if given node ID is a PLL node */
if (nid < NODE_APLL || nid > NODE_IOPLL)
if (nid < NODE_APLL || nid > NODE_IOPLL) {
return PM_RET_ERROR_ARGS;
}
/* Check if parameter ID is valid and return an error if it's not */
if (param_id >= PM_PLL_PARAM_MAX)
if (param_id >= PM_PLL_PARAM_MAX) {
return PM_RET_ERROR_ARGS;
}
/* Send request to the PMU */
PM_PACK_PAYLOAD4(payload, PM_PLL_SET_PARAMETER, nid, param_id, value);
@ -1642,12 +1667,14 @@ enum pm_ret_status pm_pll_get_parameter(enum pm_node_id nid,
uint32_t payload[PAYLOAD_ARG_CNT];
/* Check if given node ID is a PLL node */
if (nid < NODE_APLL || nid > NODE_IOPLL)
if (nid < NODE_APLL || nid > NODE_IOPLL) {
return PM_RET_ERROR_ARGS;
}
/* Check if parameter ID is valid and return an error if it's not */
if (param_id >= PM_PLL_PARAM_MAX)
if (param_id >= PM_PLL_PARAM_MAX) {
return PM_RET_ERROR_ARGS;
}
/* Send request to the PMU */
PM_PACK_PAYLOAD3(payload, PM_PLL_GET_PARAMETER, nid, param_id);
@ -1672,12 +1699,14 @@ enum pm_ret_status pm_pll_set_mode(enum pm_node_id nid, enum pm_pll_mode mode)
uint32_t payload[PAYLOAD_ARG_CNT];
/* Check if given node ID is a PLL node */
if (nid < NODE_APLL || nid > NODE_IOPLL)
if (nid < NODE_APLL || nid > NODE_IOPLL) {
return PM_RET_ERROR_ARGS;
}
/* Check if PLL mode is valid */
if (mode >= PM_PLL_MODE_MAX)
if (mode >= PM_PLL_MODE_MAX) {
return PM_RET_ERROR_ARGS;
}
/* Send request to the PMU */
PM_PACK_PAYLOAD3(payload, PM_PLL_SET_MODE, nid, mode);
@ -1697,8 +1726,9 @@ enum pm_ret_status pm_pll_get_mode(enum pm_node_id nid, enum pm_pll_mode *mode)
uint32_t payload[PAYLOAD_ARG_CNT];
/* Check if given node ID is a PLL node */
if (nid < NODE_APLL || nid > NODE_IOPLL)
if (nid < NODE_APLL || nid > NODE_IOPLL) {
return PM_RET_ERROR_ARGS;
}
/* Send request to the PMU */
PM_PACK_PAYLOAD2(payload, PM_PLL_GET_MODE, nid);
@ -1733,8 +1763,9 @@ enum pm_ret_status pm_register_access(unsigned int register_access_id,
if (((ZYNQMP_CSU_BASEADDR & address) != ZYNQMP_CSU_BASEADDR) &&
((CSUDMA_BASE & address) != CSUDMA_BASE) &&
((RSA_CORE_BASE & address) != RSA_CORE_BASE) &&
((PMU_GLOBAL_BASE & address) != PMU_GLOBAL_BASE))
((PMU_GLOBAL_BASE & address) != PMU_GLOBAL_BASE)) {
return PM_RET_ERROR_ACCESS;
}
switch (register_access_id) {
case CONFIG_REG_WRITE:
@ -1746,6 +1777,7 @@ enum pm_ret_status pm_register_access(unsigned int register_access_id,
default:
ret = PM_RET_ERROR_ARGS;
WARN("Unimplemented register_access call\n\r");
break;
}
return ret;
}

27
plat/xilinx/zynqmp/pm_service/pm_client.c
View File

@ -188,8 +188,9 @@ static void pm_client_set_wakeup_sources(void)
* If NODE_EXTERN could not be set as wake source, proceed with
* standard suspend (no one will wake the system otherwise)
*/
if (ret == PM_RET_SUCCESS)
if (ret == PM_RET_SUCCESS) {
return;
}
}
zeromem(&pm_wakeup_nodes_set, sizeof(pm_wakeup_nodes_set));
@ -198,8 +199,9 @@ static void pm_client_set_wakeup_sources(void)
uint32_t base_irq = reg_num << ISENABLER_SHIFT;
uint32_t reg = mmio_read_32(isenabler1 + (reg_num << 2));
if (!reg)
if (!reg) {
continue;
}
while (reg) {
enum pm_node_id node;
@ -208,8 +210,9 @@ static void pm_client_set_wakeup_sources(void)
idx = __builtin_ctz(lowest_set);
irq = base_irq + idx;
if (irq > IRQ_MAX)
if (irq > IRQ_MAX) {
break;
}
node = irq_to_pm_node(irq);
reg &= ~lowest_set;
@ -231,8 +234,9 @@ static void pm_client_set_wakeup_sources(void)
*/
const struct pm_proc *pm_get_proc(unsigned int cpuid)
{
if (cpuid < ARRAY_SIZE(pm_procs_all))
if (cpuid < ARRAY_SIZE(pm_procs_all)) {
return &pm_procs_all[cpuid];
}
return NULL;
}
@ -246,8 +250,9 @@ const struct pm_proc *pm_get_proc(unsigned int cpuid)
const struct pm_proc *pm_get_proc_by_node(enum pm_node_id nid)
{
for (size_t i = 0; i < ARRAY_SIZE(pm_procs_all); i++) {
if (nid == pm_procs_all[i].node_id)
if (nid == pm_procs_all[i].node_id) {
return &pm_procs_all[i];
}
}
return NULL;
}
@ -261,8 +266,9 @@ const struct pm_proc *pm_get_proc_by_node(enum pm_node_id nid)
static unsigned int pm_get_cpuid(enum pm_node_id nid)
{
for (size_t i = 0; i < ARRAY_SIZE(pm_procs_all); i++) {
if (pm_procs_all[i].node_id == nid)
if (pm_procs_all[i].node_id == nid) {
return i;
}
}
return UNDEFINED_CPUID;
}
@ -280,8 +286,9 @@ void pm_client_suspend(const struct pm_proc *proc, unsigned int state)
{
bakery_lock_get(&pm_client_secure_lock);
if (state == PM_STATE_SUSPEND_TO_RAM)
if (state == PM_STATE_SUSPEND_TO_RAM) {
pm_client_set_wakeup_sources();
}
/* Set powerdown request */
mmio_write_32(APU_PWRCTL, mmio_read_32(APU_PWRCTL) | proc->pwrdn_mask);
@ -320,8 +327,9 @@ void pm_client_wakeup(const struct pm_proc *proc)
{
unsigned int cpuid = pm_get_cpuid(proc->node_id);
if (cpuid == UNDEFINED_CPUID)
if (cpuid == UNDEFINED_CPUID) {
return;
}
bakery_lock_get(&pm_client_secure_lock);
@ -336,8 +344,9 @@ void pm_client_wakeup(const struct pm_proc *proc)
enum pm_ret_status pm_set_suspend_mode(uint32_t mode)
{
if ((mode != PM_SUSPEND_MODE_STD) &&
(mode != PM_SUSPEND_MODE_POWER_OFF))
(mode != PM_SUSPEND_MODE_POWER_OFF)) {
return PM_RET_ERROR_ARGS;
}
suspend_mode = mode;
return PM_RET_SUCCESS;

8
plat/xilinx/zynqmp/sip_svc_setup.c
View File

@ -13,9 +13,9 @@
#include "pm_svc_main.h"
/* SMC function IDs for SiP Service queries */
#define ZYNQMP_SIP_SVC_CALL_COUNT 0x8200ff00
#define ZYNQMP_SIP_SVC_UID 0x8200ff01
#define ZYNQMP_SIP_SVC_VERSION 0x8200ff03
#define ZYNQMP_SIP_SVC_CALL_COUNT U(0x8200ff00)
#define ZYNQMP_SIP_SVC_UID U(0x8200ff01)
#define ZYNQMP_SIP_SVC_VERSION U(0x8200ff03)
/* SiP Service Calls version numbers */
#define SIP_SVC_VERSION_MAJOR 0
@ -100,6 +100,6 @@ DECLARE_RT_SVC(
sip_svc,
OEN_SIP_START,
OEN_SIP_END,
SMC_TYPE_FAST,
(uint8_t)SMC_TYPE_FAST,
sip_svc_setup,
sip_svc_smc_handler);

22
plat/xilinx/zynqmp/zynqmp_ipi.c
View File

@ -25,67 +25,67 @@ const static struct ipi_config zynqmp_ipi_table[] = {
/* APU IPI */
{
.ipi_bit_mask = 0x1,
.ipi_reg_base = 0xFF300000,
.ipi_reg_base = 0xFF300000U,
.secure_only = 0,
},
/* RPU0 IPI */
{
.ipi_bit_mask = 0x100,
.ipi_reg_base = 0xFF310000,
.ipi_reg_base = 0xFF310000U,
.secure_only = 0,
},
/* RPU1 IPI */
{
.ipi_bit_mask = 0x200,
.ipi_reg_base = 0xFF320000,
.ipi_reg_base = 0xFF320000U,
.secure_only = 0,
},
/* PMU0 IPI */
{
.ipi_bit_mask = 0x10000,
.ipi_reg_base = 0xFF330000,
.ipi_reg_base = 0xFF330000U,
.secure_only = IPI_SECURE_MASK,
},
/* PMU1 IPI */
{
.ipi_bit_mask = 0x20000,
.ipi_reg_base = 0xFF331000,
.ipi_reg_base = 0xFF331000U,
.secure_only = 0,
},
/* PMU2 IPI */
{
.ipi_bit_mask = 0x40000,
.ipi_reg_base = 0xFF332000,
.ipi_reg_base = 0xFF332000U,
.secure_only = IPI_SECURE_MASK,
},
/* PMU3 IPI */
{
.ipi_bit_mask = 0x80000,
.ipi_reg_base = 0xFF333000,
.ipi_reg_base = 0xFF333000U,
.secure_only = IPI_SECURE_MASK,
},
/* PL0 IPI */
{
.ipi_bit_mask = 0x1000000,
.ipi_reg_base = 0xFF340000,
.ipi_reg_base = 0xFF340000U,
.secure_only = 0,
},
/* PL1 IPI */
{
.ipi_bit_mask = 0x2000000,
.ipi_reg_base = 0xFF350000,
.ipi_reg_base = 0xFF350000U,
.secure_only = 0,
},
/* PL2 IPI */
{
.ipi_bit_mask = 0x4000000,
.ipi_reg_base = 0xFF360000,
.ipi_reg_base = 0xFF360000U,
.secure_only = 0,
},
/* PL3 IPI */
{
.ipi_bit_mask = 0x8000000,
.ipi_reg_base = 0xFF370000,
.ipi_reg_base = 0xFF370000U,
.secure_only = 0,
},
};

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