rcar_gen3: drivers: ddr_b: Update DDR setting for H3, M3, M3N

[IPL/DDR]
- Update H3, M3, M3N DDR setting rev.0.37.

Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I072c0f61cd896e74e4e1eee39d313f82cf2f7295

drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c

@@ -90,7 +90,7 @@ static const struct _boardcnf *board_cnf;
 static uint32_t ddr_phyvalid;
 static uint32_t ddr_density[DRAM_CH_CNT][CS_CNT];
 static uint32_t ch_have_this_cs[CS_CNT] __aligned(64);
-static uint32_t rdqdm_dly[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9];
+static uint32_t rdqdm_dly[DRAM_CH_CNT][CSAB_CNT][SLICE_CNT * 2][9];
 static uint32_t max_density;
 static uint32_t ddr0800_mul;
 static uint32_t ddr_mul;
@@ -358,15 +358,13 @@ static void pll3_control(uint32_t high)
 	if (high) {
 		tmp_div = 3999 * brd_clkdiv * (brd_clkdiva + 1) /
 			(brd_clk * ddr_mul) / 2;
-		data_mul = (((ddr_mul * tmp_div) - 1) << 24) |
-			(brd_clkdiva << 7);
+		data_mul = ((ddr_mul * tmp_div) - 1) << 24;
 		pll3_mode = 1;
 		loop_max = 2;
 	} else {
 		tmp_div = 3999 * brd_clkdiv * (brd_clkdiva + 1) /
 			(brd_clk * ddr0800_mul) / 2;
-		data_mul = (((ddr0800_mul * tmp_div) - 1) << 24) |
-			(brd_clkdiva << 7);
+		data_mul = ((ddr0800_mul * tmp_div) - 1) << 24;
 		pll3_mode = 0;
 		loop_max = 8;
 	}
@@ -2711,8 +2709,8 @@ static void ddr_register_set(void)
 	uint32_t tmp;
 
 	for (fspwp = 1; fspwp >= 0; fspwp--) {
-		/*MR13,fspwp */
-		send_dbcmd(0x0e840d08 | (fspwp << 6));
+		/*MR13, fspwp */
+		send_dbcmd(0x0e840d08 | ((2 - fspwp) << 6));
 
 		tmp =
 		    ddrtbl_getval(_cnf_DDR_PI_REGSET,
@@ -2745,7 +2743,16 @@ static void ddr_register_set(void)
 		send_dbcmd(0x0e840e00 | tmp);
 		/* MR22 */
 		send_dbcmd(0x0e841616);
+
+		/* ZQCAL start */
+		send_dbcmd(0x0d84004F);
+
+		/* ZQLAT */
+		send_dbcmd(0x0d840051);
 	}
+
+	/* MR13, fspwp */
+	send_dbcmd(0x0e840d08);
 }
 
 /* Training handshake functions */
@@ -3038,12 +3045,6 @@ static uint32_t init_ddr(void)
 	/* MRS */
 	ddr_register_set();
 
-	/* ZQCAL start */
-	send_dbcmd(0x0d84004F);
-
-	/* ZQLAT */
-	send_dbcmd(0x0d840051);
-
 	/* Thermal sensor setting */
 	/* THCTR Bit6: PONM=0 , Bit0: THSST=1  */
 	data_l = (mmio_read_32(THS1_THCTR) & 0xFFFFFFBF) | 0x00000001;
@@ -3478,17 +3479,21 @@ static uint32_t wdqdm_man(void)
 	const uint32_t retry_max = 0x10;
 	uint32_t ch, ddr_csn, mr14_bkup[4][4];
 
-	ddr_setval_ach(_reg_PI_TDFI_WDQLVL_RW, (DBSC_DBTR(11) & 0xFF) + 12);
+	ddr_setval_ach(_reg_PI_TDFI_WDQLVL_RW,
+		       (mmio_read_32(DBSC_DBTR(11)) & 0xFF) + 19);
 	if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) ||
 	    (prr_product == PRR_PRODUCT_M3N) ||
 	    (prr_product == PRR_PRODUCT_V3H)) {
+		ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR_F0,
+			       (mmio_read_32(DBSC_DBTR(12)) & 0xFF) + 10);
 		ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR_F1,
-			       (DBSC_DBTR(12) & 0xFF) + 1);
+			       (mmio_read_32(DBSC_DBTR(12)) & 0xFF) + 10);
 	} else {
 		ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR,
-			       (DBSC_DBTR(12) & 0xFF) + 1);
+			       (mmio_read_32(DBSC_DBTR(12)) & 0xFF) + 10);
 	}
-	ddr_setval_ach(_reg_PI_TRFC_F1, (DBSC_DBTR(13) & 0x1FF));
+	ddr_setval_ach(_reg_PI_TRFC_F0, mmio_read_32(DBSC_DBTR(13)) & 0x1FF);
+	ddr_setval_ach(_reg_PI_TRFC_F1, mmio_read_32(DBSC_DBTR(13)) & 0x1FF);
 
 	retry_cnt = 0;
 	err = 0;

drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h

@@ -5,7 +5,7 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#define RCAR_DDR_VERSION	"rev.0.36"
+#define RCAR_DDR_VERSION	"rev.0.37"
 #define DRAM_CH_CNT		0x04
 #define SLICE_CNT		0x04
 #define CS_CNT			0x02

drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h

@@ -104,7 +104,7 @@ static const uint32_t DDR_PHY_SLICE_REGSET_H3[DDR_PHY_SLICE_REGSET_NUM_H3] = {
 	/*044d*/ 0x00000200,
 	/*044e*/ 0x01000000,
 	/*044f*/ 0x00000200,
-	/*0450*/ 0x4041a141,
+	/*0450*/ 0x4041a151,
 	/*0451*/ 0xc00141a0,
 	/*0452*/ 0x0e0100c0,
 	/*0453*/ 0x0010000c,

drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h

@@ -114,7 +114,7 @@ static const uint32_t DDR_PHY_SLICE_REGSET_H3VER2
 	/*0456*/ 0x01000000,
 	/*0457*/ 0x00000200,
 	/*0458*/ 0x00000004,
-	/*0459*/ 0x4041a141,
+	/*0459*/ 0x4041a151,
 	/*045a*/ 0xc00141a0,
 	/*045b*/ 0x0e0000c0,
 	/*045c*/ 0x0010000c,

drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h

@@ -105,7 +105,7 @@ static const uint32_t DDR_PHY_SLICE_REGSET_M3[DDR_PHY_SLICE_REGSET_NUM_M3] = {
 	/*084e*/ 0x00000000,
 	/*084f*/ 0x00010000,
 	/*0850*/ 0x00000200,
-	/*0851*/ 0x4041a141,
+	/*0851*/ 0x4041a151,
 	/*0852*/ 0xc00141a0,
 	/*0853*/ 0x0e0100c0,
 	/*0854*/ 0x0010000c,

drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h

@@ -115,7 +115,7 @@ static const uint32_t DDR_PHY_SLICE_REGSET_M3N[DDR_PHY_SLICE_REGSET_NUM_M3N] = {
 	/*0858*/ 0x01000000,
 	/*0859*/ 0x00000200,
 	/*085a*/ 0x00000004,
-	/*085b*/ 0x4041a141,
+	/*085b*/ 0x4041a151,
 	/*085c*/ 0x0141c0a0,
 	/*085d*/ 0x0000c0c0,
 	/*085e*/ 0x0e0c000e,