Browse Source
* changes: fdts: stm32mp1: realign device tree files with internal devs stm32mp1: increase device tree size to 20kB stm32mp1: make dt_get_stdout_node_offset() static stm32mp1: use unsigned values for SDMMC defines stm32mp1: remove useless LIBFDT_SRCS from PLAT_BL_COMMON_SOURCES stm32mp1: update doc for U-Boot compilation stm32mp1: add general SYSCFG management stm32mp1: move stm32_get_gpio_bank_clock() to private file clk: stm32mp1: correctly handle Clock Spreading Generator clk: stm32mp1: use defines for mask values in stm32mp1_clk_sel array clk: stm32mp1: move oscillator functions to generic file arch: add some defines for generic timer registerspull/1931/head
John Tsichritzis
5 years ago
committed by
TrustedFirmware Code Review
TrustedFirmware Code Review
26 changed files with 773 additions and 342 deletions
@ -1,167 +0,0 @@ |
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/*
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* Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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#include <errno.h> |
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#include <libfdt.h> |
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#include <platform_def.h> |
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#include <drivers/st/stm32_gpio.h> |
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#include <drivers/st/stm32mp_clkfunc.h> |
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#include <drivers/st/stm32mp1_clk.h> |
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#include <drivers/st/stm32mp1_clkfunc.h> |
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#include <dt-bindings/clock/stm32mp1-clksrc.h> |
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const char *stm32mp_osc_node_label[NB_OSC] = { |
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[_LSI] = "clk-lsi", |
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[_LSE] = "clk-lse", |
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[_HSI] = "clk-hsi", |
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[_HSE] = "clk-hse", |
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[_CSI] = "clk-csi", |
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[_I2S_CKIN] = "i2s_ckin", |
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}; |
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/*
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* Get the frequency of an oscillator from its name in device tree. |
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* @param name: oscillator name |
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* @param freq: stores the frequency of the oscillator |
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* @return: 0 on success, and a negative FDT/ERRNO error code on failure. |
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*/ |
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int fdt_osc_read_freq(const char *name, uint32_t *freq) |
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{ |
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int node, subnode; |
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void *fdt; |
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if (fdt_get_address(&fdt) == 0) { |
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return -ENOENT; |
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} |
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node = fdt_path_offset(fdt, "/clocks"); |
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if (node < 0) { |
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return -FDT_ERR_NOTFOUND; |
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} |
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fdt_for_each_subnode(subnode, fdt, node) { |
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const char *cchar; |
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int ret; |
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cchar = fdt_get_name(fdt, subnode, &ret); |
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if (cchar == NULL) { |
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return ret; |
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} |
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if (strncmp(cchar, name, (size_t)ret) == 0) { |
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const fdt32_t *cuint; |
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cuint = fdt_getprop(fdt, subnode, "clock-frequency", |
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&ret); |
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if (cuint == NULL) { |
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return ret; |
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} |
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*freq = fdt32_to_cpu(*cuint); |
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return 0; |
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} |
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} |
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/* Oscillator not found, freq=0 */ |
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*freq = 0; |
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return 0; |
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} |
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/*
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* Check the presence of an oscillator property from its id. |
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* @param osc_id: oscillator ID |
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* @param prop_name: property name |
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* @return: true/false regarding search result. |
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*/ |
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bool fdt_osc_read_bool(enum stm32mp_osc_id osc_id, const char *prop_name) |
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{ |
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int node, subnode; |
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void *fdt; |
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if (fdt_get_address(&fdt) == 0) { |
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return false; |
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} |
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if (osc_id >= NB_OSC) { |
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return false; |
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} |
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node = fdt_path_offset(fdt, "/clocks"); |
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if (node < 0) { |
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return false; |
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} |
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fdt_for_each_subnode(subnode, fdt, node) { |
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const char *cchar; |
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int ret; |
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cchar = fdt_get_name(fdt, subnode, &ret); |
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if (cchar == NULL) { |
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return false; |
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} |
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if (strncmp(cchar, stm32mp_osc_node_label[osc_id], |
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(size_t)ret) != 0) { |
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continue; |
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} |
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if (fdt_getprop(fdt, subnode, prop_name, NULL) != NULL) { |
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return true; |
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} |
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} |
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return false; |
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} |
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/*
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* Get the value of a oscillator property from its ID. |
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* @param osc_id: oscillator ID |
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* @param prop_name: property name |
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* @param dflt_value: default value |
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* @return oscillator value on success, default value if property not found. |
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*/ |
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uint32_t fdt_osc_read_uint32_default(enum stm32mp_osc_id osc_id, |
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const char *prop_name, uint32_t dflt_value) |
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{ |
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int node, subnode; |
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void *fdt; |
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if (fdt_get_address(&fdt) == 0) { |
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return dflt_value; |
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} |
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if (osc_id >= NB_OSC) { |
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return dflt_value; |
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} |
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node = fdt_path_offset(fdt, "/clocks"); |
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if (node < 0) { |
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return dflt_value; |
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} |
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fdt_for_each_subnode(subnode, fdt, node) { |
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const char *cchar; |
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int ret; |
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cchar = fdt_get_name(fdt, subnode, &ret); |
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if (cchar == NULL) { |
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return dflt_value; |
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} |
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if (strncmp(cchar, stm32mp_osc_node_label[osc_id], |
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(size_t)ret) != 0) { |
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continue; |
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} |
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return fdt_read_uint32_default(subnode, prop_name, dflt_value); |
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} |
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return dflt_value; |
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} |
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@ -1,33 +0,0 @@ |
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/*
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* Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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#ifndef STM32MP1_CLKFUNC_H |
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#define STM32MP1_CLKFUNC_H |
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#include <stdbool.h> |
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#include <libfdt.h> |
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enum stm32mp_osc_id { |
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_HSI, |
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_HSE, |
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_CSI, |
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_LSI, |
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_LSE, |
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_I2S_CKIN, |
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NB_OSC, |
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_UNKNOWN_OSC_ID = 0xFF |
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}; |
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extern const char *stm32mp_osc_node_label[NB_OSC]; |
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int fdt_osc_read_freq(const char *name, uint32_t *freq); |
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bool fdt_osc_read_bool(enum stm32mp_osc_id osc_id, const char *prop_name); |
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uint32_t fdt_osc_read_uint32_default(enum stm32mp_osc_id osc_id, |
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const char *prop_name, |
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uint32_t dflt_value); |
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#endif /* STM32MP1_CLKFUNC_H */ |
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@ -0,0 +1,180 @@ |
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/*
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* Copyright (c) 2019, STMicroelectronics - All Rights Reserved |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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#include <platform_def.h> |
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#include <common/debug.h> |
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#include <drivers/st/bsec.h> |
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#include <drivers/st/stpmic1.h> |
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#include <lib/mmio.h> |
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#include <stm32mp_dt.h> |
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#include <stm32mp1_private.h> |
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/*
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* SYSCFG REGISTER OFFSET (base relative) |
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*/ |
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#define SYSCFG_BOOTR 0x00U |
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#define SYSCFG_IOCTRLSETR 0x18U |
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#define SYSCFG_ICNR 0x1CU |
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#define SYSCFG_CMPCR 0x20U |
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#define SYSCFG_CMPENSETR 0x24U |
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/*
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* SYSCFG_BOOTR Register |
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*/ |
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#define SYSCFG_BOOTR_BOOT_MASK GENMASK(2, 0) |
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#define SYSCFG_BOOTR_BOOTPD_MASK GENMASK(6, 4) |
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#define SYSCFG_BOOTR_BOOTPD_SHIFT 4 |
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/*
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* SYSCFG_IOCTRLSETR Register |
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*/ |
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#define SYSCFG_IOCTRLSETR_HSLVEN_TRACE BIT(0) |
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#define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI BIT(1) |
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#define SYSCFG_IOCTRLSETR_HSLVEN_ETH BIT(2) |
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#define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC BIT(3) |
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#define SYSCFG_IOCTRLSETR_HSLVEN_SPI BIT(4) |
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/*
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* SYSCFG_ICNR Register |
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*/ |
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#define SYSCFG_ICNR_AXI_M9 BIT(9) |
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/*
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* SYSCFG_CMPCR Register |
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*/ |
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#define SYSCFG_CMPCR_SW_CTRL BIT(1) |
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#define SYSCFG_CMPCR_READY BIT(8) |
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#define SYSCFG_CMPCR_RANSRC GENMASK(19, 16) |
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#define SYSCFG_CMPCR_RANSRC_SHIFT 16 |
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#define SYSCFG_CMPCR_RAPSRC GENMASK(23, 20) |
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#define SYSCFG_CMPCR_ANSRC_SHIFT 24 |
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/*
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* SYSCFG_CMPENSETR Register |
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*/ |
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#define SYSCFG_CMPENSETR_MPU_EN BIT(0) |
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void stm32mp1_syscfg_init(void) |
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{ |
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uint32_t bootr; |
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uint32_t otp = 0; |
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uint32_t vdd_voltage; |
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uintptr_t syscfg_base = dt_get_syscfg_base(); |
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/*
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* Interconnect update : select master using the port 1. |
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* LTDC = AXI_M9. |
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*/ |
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mmio_write_32(syscfg_base + SYSCFG_ICNR, SYSCFG_ICNR_AXI_M9); |
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/* Disable Pull-Down for boot pin connected to VDD */ |
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bootr = mmio_read_32(syscfg_base + SYSCFG_BOOTR) & |
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SYSCFG_BOOTR_BOOT_MASK; |
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mmio_clrsetbits_32(syscfg_base + SYSCFG_BOOTR, SYSCFG_BOOTR_BOOTPD_MASK, |
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bootr << SYSCFG_BOOTR_BOOTPD_SHIFT); |
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/*
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* High Speed Low Voltage Pad mode Enable for SPI, SDMMC, ETH, QSPI |
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* and TRACE. Needed above ~50MHz and conditioned by AFMUX selection. |
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* It could be disabled for low frequencies or if AFMUX is selected |
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* but the function is not used, typically for TRACE. |
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* If high speed low voltage pad mode is node enable, platform will |
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* over consume. |
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* |
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* WARNING: |
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* Enabling High Speed mode while VDD > 2.7V |
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* with the OTP product_below_2v5 (OTP 18, BIT 13) |
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* erroneously set to 1 can damage the SoC! |
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* => TF-A enables the low power mode only if VDD < 2.7V (in DT) |
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* but this value needs to be consistent with board design. |
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*/ |
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if (bsec_read_otp(&otp, HW2_OTP) != BSEC_OK) { |
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panic(); |
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} |
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otp = otp & HW2_OTP_PRODUCT_BELOW_2V5; |
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/* Get VDD supply */ |
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vdd_voltage = dt_get_pwr_vdd_voltage(); |
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/* Check if VDD is Low Voltage */ |
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if (vdd_voltage == 0U) { |
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WARN("VDD unknown"); |
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} else if (vdd_voltage < 2700000U) { |
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mmio_write_32(syscfg_base + SYSCFG_IOCTRLSETR, |
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SYSCFG_IOCTRLSETR_HSLVEN_TRACE | |
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SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI | |
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SYSCFG_IOCTRLSETR_HSLVEN_ETH | |
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SYSCFG_IOCTRLSETR_HSLVEN_SDMMC | |
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SYSCFG_IOCTRLSETR_HSLVEN_SPI); |
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if (otp == 0U) { |
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INFO("Product_below_2v5=0: HSLVEN protected by HW\n"); |
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} |
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} else { |
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if (otp != 0U) { |
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ERROR("Product_below_2v5=1:\n"); |
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ERROR("\tHSLVEN update is destructive,\n"); |
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ERROR("\tno update as VDD > 2.7V\n"); |
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panic(); |
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} |
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} |
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stm32mp1_syscfg_enable_io_compensation(); |
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} |
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void stm32mp1_syscfg_enable_io_compensation(void) |
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{ |
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uintptr_t syscfg_base = dt_get_syscfg_base(); |
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/*
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* Activate automatic I/O compensation. |
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* Warning: need to ensure CSI enabled and ready in clock driver. |
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* Enable non-secure clock, we assume non-secure is suspended. |
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*/ |
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stm32mp1_clk_enable_non_secure(SYSCFG); |
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mmio_setbits_32(syscfg_base + SYSCFG_CMPENSETR, |
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SYSCFG_CMPENSETR_MPU_EN); |
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while ((mmio_read_32(syscfg_base + SYSCFG_CMPCR) & |
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SYSCFG_CMPCR_READY) == 0U) { |
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; |
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} |
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mmio_clrbits_32(syscfg_base + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL); |
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} |
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void stm32mp1_syscfg_disable_io_compensation(void) |
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{ |
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uintptr_t syscfg_base = dt_get_syscfg_base(); |
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uint32_t value; |
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/*
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* Deactivate automatic I/O compensation. |
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* Warning: CSI is disabled automatically in STOP if not |
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* requested for other usages and always OFF in STANDBY. |
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* Disable non-secure SYSCFG clock, we assume non-secure is suspended. |
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*/ |
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value = mmio_read_32(syscfg_base + SYSCFG_CMPCR) >> |
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SYSCFG_CMPCR_ANSRC_SHIFT; |
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mmio_clrbits_32(syscfg_base + SYSCFG_CMPCR, |
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SYSCFG_CMPCR_RANSRC | SYSCFG_CMPCR_RAPSRC); |
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value = mmio_read_32(syscfg_base + SYSCFG_CMPCR) | |
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(value << SYSCFG_CMPCR_RANSRC_SHIFT); |
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mmio_write_32(syscfg_base + SYSCFG_CMPCR, value); |
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mmio_setbits_32(syscfg_base + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL); |
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mmio_clrbits_32(syscfg_base + SYSCFG_CMPENSETR, |
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SYSCFG_CMPENSETR_MPU_EN); |
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stm32mp1_clk_disable_non_secure(SYSCFG); |
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} |
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