Commit 4242262(feat(simd):add sve state to simd ctxt struct)
introduced the CTX_INCLUDE_SVE_REGS build flag that needs to be set
if SVE is enabled for more than one world, which is the case for
RD-V3. This build flag enables SVE registers to be included when
saving and restoring the CPU context.
Change-Id: Ic491939061e42e8c87a805ded99e271308f90352
Signed-off-by: Gautham Ravichandran <gautham.ravichandran@arm.com>
Set the Make flags for TF-A to be able to enable SME and SME2 features.
Note that we enable these architectural features for both the secure and
non-secure worlds, which is required on TC4.
In the case of the non-secure world, we specify a value of 2 for the
flag which specifies that TF-A should check the feature register to
ensure that the feature is present before enabling it. This allows these
flags to be compatible with all platforms and stops TF-A doing anything
different if it does not detect that the feature is present.
Change-Id: I51f8c7e3eb1cf06767f4b155c93269e1f129f730
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
Add new include (specific to TC4) to the TC platform file which
specifies the system generic timer base address and is used by the TF-a
for use as system counters.
Note that this include must come before arm_def.h. This is required
as it checks if ARM_SYS_CNTCTL macros are defined before defining
its own macros.
Change-Id: I56861e5737271b29f09c75d962533be620766b52
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
Add basic support for TARGET_VERSION=4. It extends the existing 'if'
statements in the Makefile and the header to allow them to take the
value of 4 and also specifies the SCMI platform info to use for TC4.
Change-Id: I8d8257671314277a133e88ef65fae8fada93d00e
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
This change fixes several breakages that were introduced in some build
configurations by the introduction of the cot-dt2c tool.
Some Python environments cannot be managed directly via `pip`, and
invocations of `make`, including `make distclean`, would cause errors
along the lines of:
error: externally-managed-environment
× This environment is externally managed
╰─> To install Python packages system-wide, try apt install
python3-xyz, where xyz is the package you are trying to
install.
This change has been resolved by ensuring that calls to the cot-dt2c
tool from the build system happen exclusively through Poetry, which
automatically sets up a virtual environment that *can* be modified.
Some environments saw the following error when building platforms where
the cot-dt2c tool was used:
make: *** No rule to make target '<..>/debug/bl2_cot.c', needed
by '<..>/debug/bl2/bl2_cot.o'. Stop.
Additionally, environments with a more recent version of Python saw the
following error:
File "<...>/lib/python3.12/site-packages/cot_dt2c/cot_parser.py",
line 637, in img_to_c
if ifdef:
^^^^^
NameError: name 'ifdef' is not defined
Both of these errors have now been resolved by modifications to the
build system and the cot-dt2c tool to enable preprocessing of the device
tree source file before it is processed by the tool.
As a consequence of this change, the `pydevicetree` library is no longer
vendored into the repository tree, and we instead pull it in via a
dependency in Poetry.
This change also resolves several MyPy warnings and errors related to
missing type hints.
Change-Id: I72b2d01caca3fcb789d3fe2549f318a9c92d77d1
Signed-off-by: Chris Kay <chris.kay@arm.com>
When trying to build for the Corstone-1000 platform without specifying a
valid TARGET_PLATFORM value, the "make" call reports a Makefile error
instead of the expected error messages pointing to the variable
omission:
====================
platform.mk: *** recipe commences before first target. Stop.
====================
This is due to the make's infamous special handling of the tab
character.
Fix the error report by replacing the tab with spaces.
Change-Id: I38264b6731793e5d5b929c189bb963e55bd5ce2d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* Currently, EL1 context is included in cpu_context_t by default
for all the build configurations.
As part of the cpu context structure, we hold a copy of EL1, EL2
system registers, per world per PE. This context structure is
enormous and will continue to grow bigger with the addition of
new features incorporating new registers.
* Ideally, EL3 should save and restore the system registers at its next
lower exception level, which is EL2 in majority of the configurations.
* This patch aims at optimising the memory allocation in cases, when
the members from the context structure are unused. So el1 system
register context must be omitted when lower EL is always x-EL2.
* "CTX_INCLUDE_EL2_REGS" is the internal build flag which gets set,
when SPD=spmd and SPMD_SPM_AT_SEL2=1 or ENABLE_RME=1.
It indicates, the system registers at EL2 are context switched for
the respective build configuration. Here, there is no need to save
and restore EL1 system registers, while x-EL2 is enabled.
Henceforth, this patch addresses this issue, by taking out the EL1
context at all possible places, while EL2 (CTX_INCLUDE_EL2_REGS) is
enabled, there by saving memory.
Change-Id: Ifddc497d3c810e22a15b1c227a731bcc133c2f4a
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
SCTLR_EL1 and TCR_EL1 regs are included either as part of errata
"ERRATA_SPECULATIVE_AT" or under el1_sysregs_t context structure.
The code to write and read into these context entries, looks
repetitive and is invoked at most places.
This section is refactored to bring them under a static procedure,
keeping the code neat and easier to maintain.
Change-Id: Ib0d8c51bee09e1600c5baaa7f9745083dca9fee1
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
This patch demonstrates the capability of SEPARATE_SIMD_SECTION build
flag through which the memory intensive SIMD context data structures
are allocated in a separate section withtin the TZC DRAM space.
Change-Id: Idf3f232a7960a8f84f279d496c76953a6dad2009
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
This patch adds the SP partition manifest to boot Cactus SP on
EL3 SPMC to be used with FVP platform.
Change-Id: I88b36f6ac21ebba7fa93aef75dad74bb9ee5c944
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Illegal combinations of build flags associated with SIMD context
management are flagged by the build system.
Change-Id: I3192af3889e1e864c7875778616e167ba6894195
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Enable following erratas as per the TARGET_PLATFORM of TC
- ERRATA_A520_2938996
- ERRATA_X4_2726228
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ia552473740c34867dd9fd619faf378adcb784821
Integrate the cot-dt2c tool into build process
for TBBR configuration
Change-Id: I42ccbc96c5c8fd21266200e427306a80236a78aa
Signed-off-by: Xialin Liu <Xialin.Liu@ARM.com>
Change the makefile to call the cot-dt2c tool
during the build for Arm platform
Change-Id: Idb7c02cca6b9ddd87f575a42c88e7b2660b896e0
Signed-off-by: Xialin Liu <Xialin.Liu@ARM.com>
Separate the bl1 and bl2 CoT into individual C files for the
upcoming tool, i.e. the CoT device tree-to-source file generator.
Change-Id: I0d24791991b3539c7aef9a562920dc62fecdc69a
Signed-off-by: Xialin Liu <Xialin.Liu@ARM.com>
Align the naming of nv_counter to nv_ctr in the DTBs
so that they match with the static C files. Update the
binding documentation accordingly. This renaming is beneficial
for the upcoming conversion tool that will convert CoT DT files
to C files.
Change-Id: If65d51ad9fc6445b1ae9937f1691becf8742cf01
Signed-off-by: Xialin Liu <Xialin.Liu@ARM.com>
As the NEED_* are internal flags used in the build system and are not
meant to be used by platforms, remove them from the RD-V3 makefile.
Signed-off-by: Jaylyn Ren <Jaylyn.Ren2@arm.com>
Change-Id: If7144b9d72c16e8025f929f2546abd96194615ce
NI-Tower's component's registers are need to be accessed from
kernel NI-PMU driver so enable NS access to it.
Change-Id: I83a8b3a1d2778baf767ff93263e246d127ef8114
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
The SRAM (CVM) memory layout was outdated in the platform_defs.h of
the Corstone-1000 platform. Updated it to list every bootloaders and
to be aligned with the implementation. Also added the starting (base)
addresses of each partition.
Change-Id: Ie8e8416ee2650ff25a8d4c61d8d9af789bc639c1
Signed-off-by: Bence Balogh <bence.balogh@arm.com>
Corstone1000 does not properly clean the cache and disable gic interrupts
before the reset. This causes a race condition especially in FVP after
reset. This adds proper sequence before resetting the platform.
Change-Id: I22791eec2ec0ca61d201d8a745972a351248aa3d
Signed-off-by: Emekcan Aras <Emekcan.Aras@arm.com>
Refactor DT relocation logic from BL2 to BL31 for non-secure DRAM.
Previously, BL2 was responsible for copying the DT into SRAM and DRAM,
resulting in duplicate code in BL31 to cater for the `RESET_TO_BL31`
case. By moving the re-location logic to BL31, we simplify handling of
the non-secure DT and TL.
Change-Id: Id239f9410669afe4b223fa8d8bb093084a0e5e1b
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Use the designated macro to accurately set the signature within the
parameters transferred from BL33 to the non-secure payload.
Change-Id: Id91319121a70b2c72f8489450f191ca4f129cfcb
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
After enabling additional features in Trusted Services, the size of BL32
image (OP-TEE + Trusted Services SPs) is larger now. To create more space
in secure RAM for BL32 image, this patch removes NS_SHARED_RAM region
which is not currently used by corstone1000 platform.
Change-Id: I1e9468fd2dcb66b4d21fce245097ba51331ec54d
Signed-off-by: Emekcan Aras <Emekcan.Aras@arm.com>
Passes spsr value for BL33 (U-Boot) explicitly between different boot
stages. This information is needed in order to boot properly.
Change-Id: I06b5b750f963f8609e00ff6bf2838bac0f8b7b28
Signed-off-by: Emekcan Aras <Emekcan.Aras@arm.com>
To support UEFI secure variable service,
StandaloneMm which runs in BL32 should know flash areas.
Add flash memory areas and system register region
so that StandaloneMm access to flash storages.
Change-Id: I803bda9664a17a0b978ebff90974eaf5442a91cd
Signed-off-by: levi.yun <yeoreum.yun@arm.com>
OP-TEE enables the use case of a secure interrupt triggered by the UART
driver. This interrupt is routed by FFA_INTERRUPT interface to OP-TEE.
Define the UART interrupt in the FF-A device region node.
Without this change, OPTEE panics at the boot with the following:
| I/TC: No non-secure external DT
| I/TC: manifest DT found
| I/TC: OP-TEE version: 4.3.0-23-gfcd8750677db
| I/TC: WARNING: This OP-TEE configuration might be insecure!
| I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html
| I/TC: Primary CPU initializing
| E/TC:0 0 assertion '!res' failed at core/drivers/hfic.c:56 <hfic_op_enable>
| E/TC:0 0 Panic at core/kernel/assert.c:28 <_assert_break>
| E/TC:0 0 TEE load address @ 0x6284000
Change-Id: Icddcdfd032315aeee65ba3100f3a6b470a74435d
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Currently the EL1 part of the context structure (el1_sysregs_t),
is coupled with feature flags reducing the context memory allocation
for platforms, that don't enable/support all the architectural
features at once.
Similar to the el2 context optimization commit-"d6af234" this patch
further improves this section by converting the assembly context-offset
entries into a c structure. It relies on garbage collection of the
linker removing unreferenced structures from memory, as well as aiding
in readability and future maintenance. Additionally, it eliminates
the #ifs usage in 'context_mgmt.c' source file.
Change-Id: If6075931cec994bc89231241337eccc7042c5ede
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
* Currently, "ERRATA_SPECUALTIVE_AT" errata is enabled by default
for few cores and they need context entries for saving and
restoring EL1 regs "SCTLR_EL1 and TCR_EL1" registers at all times.
* This prevents the mechanism of decoupling EL1 and EL2 registers,
as EL3 firmware shouldn't be handling both simultaneously.
* Depending on the build configuration either EL1 or EL2 context
structures need to included, which would result in saving a good
amount of context memory.
* In order to achieve this it's essential to have explicit context
entries for registers supporting "ERRATA_SPECULATIVE_AT".
* This patch adds two context entries under "errata_speculative_at"
structure to assist this errata and thereby allows decoupling
EL1 and EL2 context structures.
Change-Id: Ia50626eea8fb64899a2e2d81622adbe07fe77d65
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
The EXTLLC bit in CPUECTLR_EL1 register indicates that an external
Last-level cache is present in the system.
This bit is not set for CPUs on TC3 platform despite there is
presence of LLC in MCN, so set them.
Change-Id: I5f889e67dce2b1d00e4ee66a8c255cf7911825b0
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
To enable device memory sharing test make memory region for UART0
and 1 a NS device region so that it can be shared by tf-a-tests
to the cactus SP.
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
Change-Id: Iadfe02a65f5d4a8b60296f07c4943dd31f201453
DSU PMU registers are write accessible in EL1 if the ACTLR_EL3[12] bit
and the ACTLR_EL2[12] bit are set to 1, and these registers are need to
be set for all cores, so set these bits in platform reset handler.
Change-Id: I1db6915939727f0909c05c8b103e37984aadb443
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
The comment for plat_reset_handler doesn't make sense. It is likely a
copy-and-paste error while adding the code, so remove it.
Change-Id: Iab8c8c799c184fa99966770d47ecb11bbc640515
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Include platform.h file in order to remove following compiler errors,
as some warnings are being treated as errors now.
error: implicit declaration of function
'plat_core_pos_by_mpidr'[-Wimplicit-function-declaration]
Change-Id: Ie223e11e138ec9b0eef7342f450b90b215a49b15
Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
This patch disables trapping to EL3 when the FEAT_FGT2
specific trap registers are accessed by setting the
SCR_EL3.FGTEn2 bit
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I6d2b614affb9067b2bc3d7bf0ae7d169d031592a
This patch enables FEAT_Debugv8p9 and prevents EL1/0 from
trapping to EL3 when accessing MDSELR_EL1 register by
setting the MDCR_EL3.EBWE bit.
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I3613af1dd8cb8c0d3c33dc959f170846c0b9695a
Provide manifest to boot OP-TEE at S-EL1 running SPMC with secure EL2
disabled and TF-A at secure EL3 running SPMD.
Change-Id: If8547b5a514fb48eec88a8d56d718f1c1591cf1f
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Update the memory size allocated to optee at EL1 to 0xd80000 to match
the size specified by mem-size in optee manifest.
Change-Id: I6826a56d0f68a6a2b5181f849a741a9bf1f0829b
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
The memory regions that Linux kernel can share including TX/RX buffers
encompass the entire DRAM. Update it accordingly. Without this,
when the Linux kernel call FFA_RXTX_MAP, it fails sometime and the
below error from the secure world appears:
| ERROR: arch_other_world_vm_configure_rxtx_map: send page is invalid
| (expected 0x87, got 0x7c)
Change-Id: Idb40907af2e0c1d4e60979b4948db2fc70971145
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
OPTEE now supports FF-A v1.1, lets us bump the FF-A version in the
OPTEE FF-A manifest.
Change-Id: Ia51cbe1af619895945240004a4163a4c4bda2ee5
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Without the mem-size attribute, the OPTEE boot panics with below
error:
| get_sec_mem_from_manifest:1594 Can't read "mem-size" from FF-A
| manifest at 0x6281000: error -1
| Panic at core/arch/arm/kernel/boot.c:1596 <get_sec_mem_from_manifest>
| TEE load address @ 0x6284000
| Call stack:
| 0x0628c7fc
| 0x06298788
| 0x0628c480
Adding the mem-size attribute fixes the boot. This is OPTEE specific
extension.
Change-Id: I2801c8b4a89cffafff14c788319ad106b03ffef0
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Without the FF-A manifest boot info node, the OPTEE boot as S-EL1 VM
crashes currently with the below error:
| WARNING: Stage-2 page fault: pc=0x628c41c, vmid=0x8001, vcpu=0,
| vaddr=0xd00000, ipaddr=0xd00000, mode=0x1 0x7c
| NOTICE: Injecting Data Abort exception into VM 0x8001.
Adding the boot info node fixes the OPTEE boot.
While at it, also update copyright year in the file.
Change-Id: I1fd0bf4e38bb95deedc74fa04d1e6bb057424c04
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Arm has decided to rename RD-Fremont to RD-V3 to align with its
existing product lineup, such as RD-V1, RD-V2, etc. This change
replaces all occurences of "Fremont" with "V3" in file names and
contents.
Change-Id: I302103492f962a7ac74854633ad68701b2a7f420
Signed-off-by: Jerry Wang <Jerry.Wang4@arm.com>
Fix BL31 crashes caused by incorrect placement of firmware handoff code
within an assert. The function call has been removed from the assert to
ensure it’s executed even when assertions are disabled.
Change-Id: I668f5c08af33327e8ff0e22887c3da109bd6be31
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Keeping the MTE2 enablement under the SPMD check is breaking for FPGA
and CI test, as SPMD is absent in these cases.
Enable MTE2 unconditionally so that all the supported platforms can use
it.
Change-Id: Id86893f0e2767a8686c3dca0ea092907d5c107ba
Signed-off-by: Tintu Thomas <tintu.thomas@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
gaurav02
Jackson Cooper-Driver
Leo Yan
Chris Kay
Andre Przywara
Jayanth Dodderi Chidanand
Madhukar Pappireddy
Manish Pandey
Xialin Liu
Jaylyn Ren
Jagdish Gediya
Bence Balogh
Emekcan Aras
Harrison Mutai
Jimmy Brisson
levi.yun
Olivier Deprez
Daniel Boulby
Harsimran Singh Tungal
Arvind Ram Prakash
Sudeep Holla
Jerry Wang
Tintu Thomas