Enable NI-Tower PMU on TC3.
Change-Id: I8a4d4e31e84ab33f95bc8b7661e873cf97561b79
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
NI-Tower's component's registers are need to be accessed from
kernel NI-PMU driver so enable NS access to it.
Change-Id: I83a8b3a1d2778baf767ff93263e246d127ef8114
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
* changes:
fix(arm): move HW_CONFIG relocation into BL31
feat: add option to input attr as string of flag names
feat: add option to input text instead of tag id number
feat: add creating transfer lists from yaml files
The SRAM (CVM) memory layout was outdated in the platform_defs.h of
the Corstone-1000 platform. Updated it to list every bootloaders and
to be aligned with the implementation. Also added the starting (base)
addresses of each partition.
Change-Id: Ie8e8416ee2650ff25a8d4c61d8d9af789bc639c1
Signed-off-by: Bence Balogh <bence.balogh@arm.com>
Corstone1000 does not properly clean the cache and disable gic interrupts
before the reset. This causes a race condition especially in FVP after
reset. This adds proper sequence before resetting the platform.
Change-Id: I22791eec2ec0ca61d201d8a745972a351248aa3d
Signed-off-by: Emekcan Aras <Emekcan.Aras@arm.com>
Add the RMM option description in the build-options document.
Signed-off-by: Jaylyn Ren <Jaylyn.Ren2@arm.com>
Change-Id: Idb884e2707a2bdc686f676d16f0ff2f0e001a17d
Refactor DT relocation logic from BL2 to BL31 for non-secure DRAM.
Previously, BL2 was responsible for copying the DT into SRAM and DRAM,
resulting in duplicate code in BL31 to cater for the `RESET_TO_BL31`
case. By moving the re-location logic to BL31, we simplify handling of
the non-secure DT and TL.
Change-Id: Id239f9410669afe4b223fa8d8bb093084a0e5e1b
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Rename 'doc' group to 'docs' for consistency, this is to follow the
widely accepted convention of using plural nouns groups that contain
multiple items. This change signifies that the 'docs' group includes a
collection of documentation-related dependencies.
Also, ensure that the dependencies are actually conditionally installed
by setting the group as optional. This was missing in the original
change.
Change-Id: I07caccfb1b57bc2dc1e7596899dfb926e8a5f71a
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Use the designated macro to accurately set the signature within the
parameters transferred from BL33 to the non-secure payload.
Change-Id: Id91319121a70b2c72f8489450f191ca4f129cfcb
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
This commit adds a command create-from-yaml to tlc, which
creates a transfer list from a yaml file. It also changes
the files structure of the fixtures in the unit tests so
they are in a directory called trusted-firmware-a. This
is necessary because blob file paths in the yaml file are
relative to the root of TF-A.
The blob files are not verified by TLC, so it can be used
to load arbitrary binary information into the transfer
list. The authenticity of the transfer list must be
ensured by the loader.
Change-Id: Idf704ce5d9b7e28b31f471ac337e4aef33d0ad8a
Signed-off-by: Charlie Bareham <charlie.bareham@arm.com>
Cortex-A720 erratum 2844092 is a Cat B erratum that is present
in revisions r0p0, r0p1 and is fixed in r0p2.
The workaround is to set bit[11] of CPUACTLR4_EL1 register.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-2439421/latest
Change-Id: I3d8eacb26cba42774f1f31c3aae2a0e6fecec614
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
Cortex-X4 erratum 2816013 is a Cat B erratum that applies
to all revisions <= r0p1 and is fixed in r0p2. This erratum
is only present when memory tagging is enabled.
The workaround is to set CPUACTLR5_EL1[14] to 1.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-2432808/latest
Change-Id: I546044bde6e5eedd0abf61643d25e2dd2036df5c
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
RTD uses a mixture of poetry and pip to install packages in the build
environment. In the past it was recommended to disable poetry from
creating a fresh virtual environment. Instead, the expectation was that
poetry would be able to detect it's current virtual environment and
install the packages in the right place. This was recently updated to
allow poetry to better allow dependcy management by poetry [1]. Remove
this configuration and explicitly point Poetry to the virtual
environment.
[1] https://github.com/readthedocs/readthedocs.org/pull/11152
Change-Id: I58e49ba6f6d122e70bbcf1dbb10220881a09faf3
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
This new version uses fewer internal functions
in favour of calling equivalent mbedtls APIs.
Change-Id: I0c2c20a74687211f2d554501f57898da07b01739
Signed-off-by: Ryan Everett <ryan.everett@arm.com>
pll_reg.b.bypass equal to 1U, bypass the mpll calculating
pll_reg.b.bypass equal to 0U, need to calculate mpll
Change-Id: I6cace1509d9429a97c7c9481dc1e2e4f95134d6c
Signed-off-by: Kevin Chen <kevin_chen@aspeedtech.com>
* changes:
build: make poetry use existing lock file
feat(arm): add fw handoff support for RESET_TO_BL31
feat(tlc): add host tool for static TL generation
In sunxi_soc_fdt_fixup(), we check for the value of "ret" again, after
calling fdt_node_offset_by_phandle(), even though the error value of
that lands in "node".
Check for "node" being non-negative instead, to properly detect any
errors here.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: I57c1406388dbe11d343038da173019519e18af3e
Updated documentation for new SMC SiP calling conventions for Platform
Management specific SiP Service calls.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: Iee09d3d843c6bb3f82aad6df703542ba1eb63c6c
Currently, there is common feature check function for firmware APIs
and TF-A specific APIs. This should be separate from firmware APIs.
So add new TF-A API for feature check of TF-A specific APIs.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I5585d17fb6aa1e98989d935117cca10bdb85133e
SMC ID is fixed in new SiP SVC call format while it varies according
to PLM header in old Linux. So, enhance SIP_SVC_VERSION number to
support backward compatibility and to use full request and response
buffer from bare-metal or Linux.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I6764cc92b33b7366640f553827e80c5e97985fcf
Currently, the IDs used in PLM CMD header are mixed with SMC IDs in
TF-A which is restricting the range of IDs that can be used by PLM.
Also, the SMC call from firmware driver is passing all 7 32-bit
words in request but TF-A is not passing all of them to firmware and
TF-A passes only 4 32-bit words from firmware to Linux in response.
So, update TF-A to passthrough all PLM commands by having a single
fixed SMC ID for all PLM commands and keep the PLM header in subsequent
SMC arguments. Also, enhance size of payload argument count to support
maximum payloads in request and response buffers to transmit all the
IPI command properly.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I2601caba849bce3f294177b63baa1ad688e3c5bb
Currently, PLM IPI command supports total 8 32-bit payloads. But existing
logic to read IPI response in TF-A is trying to read 9 32-bit payloads
(ret status + 8 ret payloads) in case of IPI_CRC_CHECK enabled which is
incorrect.
So, fix logic to read only 8 32-bit payloads (ret status + 6 ret payloads + CRC)
in case when IPI_CRC_CHECK is enabled and read 7 32-bit payloads
(ret status + 5 ret payloads + CRC) in case when IPI_CRC_CHECK is disabled.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I0abca2f787cc7a66fdd5522e6bd15a9771029071
After enabling additional features in Trusted Services, the size of BL32
image (OP-TEE + Trusted Services SPs) is larger now. To create more space
in secure RAM for BL32 image, this patch removes NS_SHARED_RAM region
which is not currently used by corstone1000 platform.
Change-Id: I1e9468fd2dcb66b4d21fce245097ba51331ec54d
Signed-off-by: Emekcan Aras <Emekcan.Aras@arm.com>
Passes spsr value for BL33 (U-Boot) explicitly between different boot
stages. This information is needed in order to boot properly.
Change-Id: I06b5b750f963f8609e00ff6bf2838bac0f8b7b28
Signed-off-by: Emekcan Aras <Emekcan.Aras@arm.com>
This target can currently fail as the `$(BUILD_PLAT)` target no longer exists, as it is now `$(BUILD_PLAT)/` (with an explicit trailing slash).
Change-Id: I9172b2f51f6e02e6369f62468ea63a64ec0f6dd1
Signed-off-by: Chris Kay <chris.kay@arm.com>
This makes the build reproducible.
When `make dev-install` was run, it would ignore the existing
poetry lock file, install different versions of all the
libraries, then overwrite the lock file. Once `--no-update`
is added, it stops doing that, and installs exactly what is
in the poetry lock file.
Change-Id: If62637a40504d23deb47a05347a272e1c13bf41e
Signed-off-by: Charlie Bareham <charlie.bareham@arm.com>
Transfer List Compiler is a command line tool that enables the static
generation of TL's compliant with version 0.9 of the firmware handoff
specification. The intent of this tool is to support information passing
via the firmware handoff framework to bootloaders that run without
preceding images (i.e. `RESET_TO_BL31`).
It currently allows for TL's to be statically generated from blobs of
data, and modified by removing/adding TE's. Future work will provide
support for TL generation from configuration file.
Change-Id: Iff670842e34c9ad18eac935248ee2aece43dc533
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Co-authored-by: Charlie Bareham <charlie.bareham@arm.com>
This patch adds trbe_disable() which disables Trace buffer access
from lower ELs in all security state. This function makes Secure
state the owner of Trace buffer and access from EL2/EL1 generate
trap exceptions to EL3.
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: If3e3bd621684b3c28f44c3ed2fe3df30b143f8cd
Introduce a function to disable SPE feature for Non-secure state and do
the default setting of making Secure state the owner of profiling
buffers and trap access of profiling and profiling buffer control
registers from lower ELs to EL3.
This functionality is required to handle asymmetric cores where SPE has
to disabled at runtime.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I2f99e922e8df06bfc900c153137aef7c9dcfd759
During CPU power down, we stop the profiling by calling spe_disable()
function. From TF-A point of view, enable/disable means the avaibility
of the feature for lower EL. In this case we are not actully disabling
the feautre but stoping it before power down.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I6e3b39c5c35d330c51e7ac715446a8b36bf9531f
* changes:
feat(allwinner): adjust H616 L2 cache size in DTB
feat(allwinner): h616: add support for AXP717 PMIC
feat(allwinner): h616: add support for AXP313 PMIC
feat(allwinner): h616: add I2C PMIC support
refactor(allwinner): h616: prepare for more than one PMIC model
To support UEFI secure variable service,
StandaloneMm which runs in BL32 should know flash areas.
Add flash memory areas and system register region
so that StandaloneMm access to flash storages.
Change-Id: I803bda9664a17a0b978ebff90974eaf5442a91cd
Signed-off-by: levi.yun <yeoreum.yun@arm.com>
Jagdish Gediya
Manish V Badarkhe
Manish Pandey
Bence Balogh
Emekcan Aras
Jaylyn Ren
Harrison Mutai
Charlie Bareham
Sona Mathew
Ryan Everett
Kevin Chen
André Przywara
Jay Buddhabhatti
Jimmy Brisson
Chris Kay
Arvind Ram Prakash
levi.yun