OP-TEE enables the use case of a secure interrupt triggered by the UART
driver. This interrupt is routed by FFA_INTERRUPT interface to OP-TEE.
Define the UART interrupt in the FF-A device region node.
Without this change, OPTEE panics at the boot with the following:
| I/TC: No non-secure external DT
| I/TC: manifest DT found
| I/TC: OP-TEE version: 4.3.0-23-gfcd8750677db
| I/TC: WARNING: This OP-TEE configuration might be insecure!
| I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html
| I/TC: Primary CPU initializing
| E/TC:0 0 assertion '!res' failed at core/drivers/hfic.c:56 <hfic_op_enable>
| E/TC:0 0 Panic at core/kernel/assert.c:28 <_assert_break>
| E/TC:0 0 TEE load address @ 0x6284000
Change-Id: Icddcdfd032315aeee65ba3100f3a6b470a74435d
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
* changes:
fix(rmmd): remove the assert check for RMM_BASE
fix(std_svc): continue boot if rmmd_setup fails
fix(rmmd): ignore SMC FID when RMM image is not present
fix(rmmd): fail gracefully if RME is not enabled
fix(rmmd): handle RMMD manifest loading failure
Currently the EL1 part of the context structure (el1_sysregs_t),
is coupled with feature flags reducing the context memory allocation
for platforms, that don't enable/support all the architectural
features at once.
Similar to the el2 context optimization commit-"d6af234" this patch
further improves this section by converting the assembly context-offset
entries into a c structure. It relies on garbage collection of the
linker removing unreferenced structures from memory, as well as aiding
in readability and future maintenance. Additionally, it eliminates
the #ifs usage in 'context_mgmt.c' source file.
Change-Id: If6075931cec994bc89231241337eccc7042c5ede
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
* Currently, "ERRATA_SPECUALTIVE_AT" errata is enabled by default
for few cores and they need context entries for saving and
restoring EL1 regs "SCTLR_EL1 and TCR_EL1" registers at all times.
* This prevents the mechanism of decoupling EL1 and EL2 registers,
as EL3 firmware shouldn't be handling both simultaneously.
* Depending on the build configuration either EL1 or EL2 context
structures need to included, which would result in saving a good
amount of context memory.
* In order to achieve this it's essential to have explicit context
entries for registers supporting "ERRATA_SPECULATIVE_AT".
* This patch adds two context entries under "errata_speculative_at"
structure to assist this errata and thereby allows decoupling
EL1 and EL2 context structures.
Change-Id: Ia50626eea8fb64899a2e2d81622adbe07fe77d65
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Errata printing is done directly via generic_errata_report.
This commit removes the unused \_cpu\()_errata_report
functions for all cores, and removes errata_func from cpu_ops.
Change-Id: I04fefbde5f0ff63b1f1cd17c864557a14070d68c
Signed-off-by: Ryan Everett <ryan.everett@arm.com>
In all non-trivial cases the CPU specific errata functions
already call generic_errata_report, this cuts out the middleman
by directly calling generic_errata_report from
print_errata_status.
The CPU specific errata functions (cpu_ops->errata_func)
can now be removed from all cores, and this field can be
removed from cpu_ops.
Also removes the now unused old errata reporting
function and macros.
Change-Id: Ie4a4fd60429aca37cf434e79c0ce2992a5ff5d68
Signed-off-by: Ryan Everett <ryan.everett@arm.com>
Update Versal platform to enable runtime detection of variants instead
of relying on the build argument VERSAL_PLATFORM.
Integrate functionality for identifying the board variant during
runtime, allowing dynamic adjustment of CPU and UART clock values
accordingly.
Print the runtime board information during boot.
This advancement streamlines the build process by eliminating
dependencies on variant-specific builds, enabling the use of a single
binary for multiple variants.
Removing all the platform related constants for versal_virt,SPP,EMU as
they are not used.
Change-Id: I8c1a1d391bd1a8971addc1f56f8309a3fb75aa6d
Signed-off-by: Amey Avinash Raghatate <AmeyAvinash.Raghatate@amd.com>
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>
The EXTLLC bit in CPUECTLR_EL1 register indicates that an external
Last-level cache is present in the system.
This bit is not set for CPUs on TC3 platform despite there is
presence of LLC in MCN, so set them.
Change-Id: I5f889e67dce2b1d00e4ee66a8c255cf7911825b0
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
OP-TEE requires SGIs to be handled at S-EL1. The
Makefile was not properly setting the flag
GICV2_G0_FOR_EL3 to 0 when the SPD is OP-TEE.
Change-Id: I256afa37ddf4ad4a154c43d51807de670c3689bb
Signed-off-by: Shen Jiamin <shen_jiamin@comp.nus.edu.sg>
To enable device memory sharing test make memory region for UART0
and 1 a NS device region so that it can be shared by tf-a-tests
to the cactus SP.
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
Change-Id: Iadfe02a65f5d4a8b60296f07c4943dd31f201453
* changes:
build(deps): bump braces
build(deps): bump the pip group across 1 directory with 2 updates
build(deps): bump the pip group across 1 directory with 7 updates
A macro 'sysreg_bitfield_insert_from_gpr' is introduced for inserting
bitfield from a general register.
Change-Id: I7288a13d70d98e23dc7a93287b04b493ffce9171
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
Add DT binding for Arm DSU PMU node.
Change-Id: Iadfb5d3bb3f69c7a771516180d1c165e60eef51d
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
DSU PMU registers are write accessible in EL1 if the ACTLR_EL3[12] bit
and the ACTLR_EL2[12] bit are set to 1, and these registers are need to
be set for all cores, so set these bits in platform reset handler.
Change-Id: I1db6915939727f0909c05c8b103e37984aadb443
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
The comment for plat_reset_handler doesn't make sense. It is likely a
copy-and-paste error while adding the code, so remove it.
Change-Id: Iab8c8c799c184fa99966770d47ecb11bbc640515
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
The system register actlr_el2 can be set during CPU or platform reset
handler. E.g. on Arm Total Compute platform, the CLUSTERPMUEN bit of
actlr_el2 is set in the platform reset handler to enable the write
access to DSU PMU registers from EL1. However, as EL2 context gets
restored without saving it beforehand during jump to SPM and next NS
image, therefore, the initialized value of actlr_el2 is not retained.
To fix this issue, keep track of actlr_el2 value during the EL2 context
initialization. This applies for both secure and non-secure security
state.
Change-Id: I1bd7b984216c042c056ad20c6724bedce5a6a3e2
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
Include platform.h file in order to remove following compiler errors,
as some warnings are being treated as errors now.
error: implicit declaration of function
'plat_core_pos_by_mpidr'[-Wimplicit-function-declaration]
Change-Id: Ie223e11e138ec9b0eef7342f450b90b215a49b15
Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
According to recently firmware handsoff spec [1]'s "Register usage at handoff
boundary", Transfer List's signature value was changed from 0x40_b10b
(3 bytes) to 4a0f_b10b (4 bytes).
As updating of TL's signature, register value of x1/r1 should be:
In aarch32's r1 value should be
R1[23:0]: set to the TL signature (4a0f_b10b -> masked range value: 0f_b10b)
R1[31:24]: version of the register convention == 1
and
In aarch64's x1 value should be
X1[31:0]: set to the TL signature (4a0f_b10b)
X1[39:32]: version of the register convention == 1
X1[63:40]: MBZ
(See the [2] and [3]).
Therefore, it requires to separate mask and shift value for register
convention version field when sets each r1/x1.
This patch fix two problems:
1. breaking X1 value with updated specification in aarch64
- change of length of signature field.
2. previous error value set in R1 in arm32.
- length of signature should be 24, but it uses 32bit signature.
This change is breaking change. It requires some patch for other
softwares (u-boot[4], optee[5]).
Link: https://github.com/FirmwareHandoff/firmware_handoff [1]
Link: https://github.com/FirmwareHandoff/firmware_handoff/issues/32 [2]
Link: 5aa7aa1d3a [3]
Link: https://lists.denx.de/pipermail/u-boot/2024-July/558628.html [4]
Link: https://github.com/OP-TEE/optee_os/pull/6933 [5]
Signed-off-by: Levi Yun <yeoreum.yun@arm.com>
Change-Id: Ie417e054a7a4c192024a2679419e99efeded1705
In a system enabled with RME, the function
'xlat_get_mem_attributes_internal' fails to accurately provide
'output PA space' for Realm and Root memory because it does not
consider the 'nse' bit in page table descriptor.
This patch resolves the issue by extracting the 'nse' bit value.
As a result, it ensures correct retrieval of attributes
in RME-enabled systems while maintaining unaffected attribute
retrieval for non-RME systems.
Change-Id: If2d01545b921c9074f48c52a98027ff331e14237
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
This commit streamlines directory creation by introducing a single
pattern rule to automatically make directories for which there is a
dependency.
We currently use several macros to generate rules to create directories
upon dependence, which is a significant amount of code and a lot of
redundancy. The rule introduced by this change represents a catch-all:
any rule dependency on a path ending in a forward slash is automatically
created.
Now, rules can rely on an unordered dependency (`|`) on `$$(@D)/` which,
when secondary expansion is enabled, expands to the directory of the
target being built, e.g.:
build/main.o: main.c | $$(@D)/ # automatically creates `build/`
Change-Id: I7e554efa2ac850e779bb302fd9c7fbb239886c9f
Signed-off-by: Chris Kay <chris.kay@arm.com>
This patch removes the assert from rmmd_setup() that checks if the
RMM image PC is equal to RMM_BASE. The RMM image can be relocated to
any address in the DRAM by the previous bootloader. So, providing the
RMM base address at compile time is not feasible for such platforms.
The assert check is now replaced with a runtime check for the RMM image.
Change-Id: I568cdb6f76f41d0dcdc7a95feb75e252a7c5c930
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch allows the boot sequence to continue even if
rmmd_setup() fails. This allows platforms to use the same
RME-enabled image to support the scenarios where RMM image
is not present.
Change-Id: Ie4de15fb98ae7226eda410e15f1a650108dd8fb3
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch marks the RMM boot as failed, to ignore the SMC
FID for the RMM at runtime, if RMM image is not present on
the platform.
Change-Id: I3c19d886d32c56837a1a0d260d5204da8b2d12f1
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch converts the assert check for RME presence into
a runtime check and returns an error to fail gracefully. This
allows platforms to use the same image on boards that do not
support RME too.
Change-Id: I0cacdd7afd85ed3581e90ea81f0a51d076adb875
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch sets the rmm_boot_failed flag to true if the RMMD
manifest loading fails. This instructs the RMMD to ignore all
SMC FID for the RMM at runtime.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: If61be6200e28fcea7a5ad697393e83679f488abc
This patch is to implement Vendor Authorize Bootloader
support for Intel Agilex, Agilex5 and N5X.
Change-Id: I23bdbbe15b3732775cea028665e2efcbd04b3aff
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Agilex5 DDR base address started from 0x8000 0000.
Thus the SIP_SMC_FPGA_CONFIG_ADDR shall be offset to
0x8040 0000.
Change-Id: I33a840cb8ebbe02bc7ff9b1f5d452641af11e576
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
* changes:
feat(fvp): add SPM manifest for OP-TEE at S-EL1 without S-EL2/Hafnium
fix(fvp): update the memory size allocated to optee at EL1
fix(fvp): add DRAM memory regions that linux kernel can share
feat(fvp): update FF-A version to v1.1 supported by optee
feat(fvp): replace managed-exit with ns-interrupts-action
fix(fvp): add optee specific mem-size attribute
fix(fvp): fix the FF-A optee manifest by adding the boot info node
Hardware hdskack register does not return a correct value after
fence and drain of the bridge is done. Thus creates software
workaround.
Change-Id: I78d8ee0596c3e7bd4883bfd6e92c883b8e369c10
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
modify the print logs when an erratum workaround does not
need to be applied to a certain revision/variant of the CPU.
Change-Id: I8f60636320f617ecd4ed88ee1fbf7a3e3e4517ee
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
Enable the A53 clock at 1GHz, the maximum frequency on S32G2 SoCs.
Change-Id: Ife96792faf8f3f46965bdcf4df75fcca5e39dc6e
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Enable the PLL dividers using their memory-mapped interface. Otherwise,
the clock will not be propagated to downstream clock modules.
Change-Id: I39115cb2cb754cee87d7b6b4aa7502c3f1ef37ce
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Add the low-level implementation to enable the ARM PLL oscillator, which
is disabled by default when booting the SoC. It will be used by PLL
diviers, for which support will be added later.
Change-Id: I964fa7374ea9a08c695009176eade01003c1d6c2
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
The clock muxes will simply pass the set rate request to the clock
module connected to its source, as they do not alter the frequency.
Change-Id: I5fda8fffa0f46a4be96deac4d6a5a880c9f86ccf
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Olivier Deprez
Jayanth Dodderi Chidanand
Ryan Everett
Maheedhar Bollapalli
Manish Pandey
Manish V Badarkhe
Jagdish Gediya
Shen Jiamin
Daniel Boulby
Harsimran Singh Tungal
levi.yun
dependabot[bot]
Chris Kay
Varun Wadekar
Sieu Mun Tang
Jit Loon Lim
Madhukar Pappireddy
Sona Mathew
Ghennadi Procopciuc