arm clusterbusqos register has a default value of 0xeeeeeeee.
this may create bottleneck for other masters in system when
accessing other memories including ddr.
hence clusterbusqos is setup to lowest value 0.
Change-Id: I73d55066eb84e198c8c69593bb5700745f04f290
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
The RSE documentation includes binary and JSON dumps of the CCA platform
token. This change updates those to match the example CCA platform
token from [1], which is also the one returned by the TC and QEMU
platforms.
[1] https://review.trustedfirmware.org/c/TF-M/tf-m-tools/+/28493
Change-Id: I21048e7f995eb24212cf62fb2128b576bc11ecff
Signed-off-by: Thomas Fossati <thomas.fossati@linaro.org>
In [1], the example CCA platform token has been updated to fix a small
problem with the description of one of the software components, and to
provide a more realistic breakdown of the expected components in the CCA
TCB.
This change replaces the static CCA platform token in the Total Compute
platform.
[1] https://review.trustedfirmware.org/c/TF-M/tf-m-tools/+/28493
Change-Id: I792e693cc994fc1e856f713fd97bac4930b28e1e
Signed-off-by: Thomas Fossati <thomas.fossati@linaro.org>
* changes:
fix(st-gpio): configure each GPIO mux as secure for STM32MP2
feat(st-gpio): add set GPIO config API
fix(stm32mp1): remove unnecessary assert on GPIO_BANK_A value
refactor(st): use GPIO banks definition from bindings
feat(dt-bindings): describe ST GPIO banks and config
GPIOs are configured as secure by default on STM32MP2. The former code
is then put under #if STM32MP13 || STM32MP15. The else part is for
STM32MP2 family.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
Change-Id: I80c5944d4ae662f9e28269c3dc543b13f0e26a7b
Add get and set GPIO level from bank and pin value.
Add functions to set a pad in GPIO configuration
and to apply some settings.
Change-Id: I5e3acb5c95cd03f3e130e1a263b221b956cb3c8d
Signed-off-by: Pascal Paillet <p.paillet@st.com>
Remove assert for unexpected value of the define GPIO_BANK_A.
This check is not required as GPIO_BANK_A = 0, it can be limited to
have bank <= GPIO_BANK_K as bank is unsigned int.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I0345d56f106fcacd6a6f93281c2d9279980cd152
Describe GPIO banks configs so that it can be used in
an STM32MP device-tree file.
Signed-off-by: Pascal Paillet <p.paillet@st.com>
Change-Id: If5dd05aae314cbb3189eb02c9fe555b832ac2bdb
Since commit ec0088bbab ("feat(gpt): add support for large GPT
mappings"), the platform needs to reserve space for the bitlock,
immediately after the L0 GPT table. Add two pages to the L0 GPT reserve.
This could be optimized later by moving the bitlock somewhere else,
because it really only needs (1 << PPS.T) / (512M * 8) = 256 bytes for
the QEMU virt platform.
Fix two more comments in qemu_pas_def.h since we're here.
Change-Id: I2b0b8de38f4b5058735ed16f1cdc50e6b2d52ad9
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Most newer CPU's have DSU and CPU power control core-off bit which
means before turning off CPUs from base power controller we need to
turn individual cores off from CPU Power control.
However there are certain older CPU's that don't have DSU and
don't support CPUPWRCTRL_EL1, so populate them as a list
and ignore setting core-off bit for those older CPU's as all newer
CPU's have them.
Note: unfortunately there is no mechanism to identify if a DSU is
present and CPUPWRCTRL_EL1 is supported through any CPU control
registers and CPUPWRCTRL_EL1 is supported only for ARM64 platforms
and not available in ARM32 platforms.
Change-Id: Iba6c3c8db60dbeb177cead7ebc65df8265860da7
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Currently, during the initial bootup phase SCTLR_EL2 register
has been initialised with the endianness bit based on header
attribute evaluation at EL3.
This is not mandatorily required as TF-A by default, expects
the software at EL2 to execute in little endian format ( EE = 0).
Henceforth, this patch removes the endianness bit evaluation for
SCTLR_EL2 register and initialises with a predefined RESET value,
setting SCTLR_EL2.EE=0.
Change-Id: I53fdd5bf907cbe35c551fc03cc893821229ff807
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
This change introduces a few helper variables for dealing with verbose
and silent build modes: `silent`, `verbose`, `q` and `s`.
The `silent` and `verbose` variables are boolean values determining
whether the build system has been configured to run silently or
verbosely respectively (i.e. with `--silent` or `V=1`).
These two modes cannot be used together - if `silent` is truthy then
`verbose` is always falsy. As such:
make --silent V=1
... results in a silent build.
In addition to these boolean variables, we also introduce two new
variables - `s` and `q` - for use in rule recipes to conditionally
suppress the output of commands.
When building silently, `s` expands to a value which disables the
command that follows, and `q` expands to a value which supppresses
echoing of the command:
$(s)echo 'This command is neither echoed nor executed'
$(q)echo 'This command is executed but not echoed'
When building verbosely, `s` expands to a value which disables the
command that follows, and `q` expands to nothing:
$(s)echo 'This command is neither echoed nor executed'
$(q)echo 'This command is executed and echoed'
In all other cases, both `s` and `q` expand to a value which suppresses
echoing of the command that follows:
$(s)echo 'This command is executed but not echoed'
$(q)echo 'This command is executed but not echoed'
The `s` variable is predominantly useful for `echo` commands, where you
always want to suppress echoing of the command itself, whilst `q` is
more useful for all other commands.
Change-Id: I8d8ff6ed714d3cb401946c52955887ed7dca602b
Signed-off-by: Chris Kay <chris.kay@arm.com>
This is another small addition to the build system utlities to make it
easier to determine the truthiness of an arbitrary value.
This change adds the `bool` function, which takes a value and determines
whether the value is "truthy". We consider a value to be truthy if it is
NOT one of: "0", "n", "no", "f" or "false" (all case-insensitive).
If the value is truthy then it is returned as-is. Otherwise, no value
is returned.
Change-Id: I19347f4c3ae00a6b448514a28cc2d9d06f683f25
Signed-off-by: Chris Kay <chris.kay@arm.com>
This is a small modification to two existing functions in the build
system: `uppercase` and `lowercase`.
These functions have been moved to the common utilities makefile, and
use the `tr` tool to simplify their implementation. Behaviour is, for
virtually all use-cases, identical.
Change-Id: I0e459d92e454087e4188b2fa5968244e5db89906
Signed-off-by: Chris Kay <chris.kay@arm.com>
* changes:
feat(st-clock): use early traces
fix(st-clock): adapt order of CSS on LSE and HSE
refactor(st-clock): remove unused struct
feat(stm32mp1-fdts): remove RTC clock configuration
refactor(st-clock): move stm32mp1_clk_rcc_regs_*lock
refactor(st-clock): driver size optimization
refactor(st-clock): remove BL32 support on STM32MP13
feat(st-clock): don't gate/ungate an oscillator if it is not wired
feat(dt-bindings): add missing SPIx bus clocks
feat(stm32mp1-fdts): remove PLL1 settings
feat(st-clock): update with new bindings
feat(stm32mp1-fdts): new RCC DT bindings for STM32MP1
feat(dt-bindings): new RCC DT bindings
feat(stm32mp1): always boot at 650MHz
refactor(st-clock): remove LSEDRV_MEDIUM_HIGH for STM32MP13
fix(st-clock): display proper PLL number for STM32MP13
fix(st-clock): do not reconfigure LSE
feat(stm32mp1-fdts): move RNG1 to CSI to improve random generation
refactor(st-clock): remove unused clk function in API
refactor(st-clock): support deactivated STGEN in stm32mp_stgen_config
feat(st-clock): add function to restore generic timer rate
Improve the restart handling of DPE. In the case of a restart
scenario where only that core is restarted which executes
the DPE client, but the core executes the DPE service
remains up and running. In this case, client needs to save
a valid context handle to be able to send commands again
to the DPE service during the new boot sequence.
BL1 saves a valid parent context handle to SDS
before passing the execution to BL2. This handle
can be used in case of a restart scenario when AP
is restarted but RSE is not. Because in that case
RSE does not save an initial context handle to SDS,
which meant to be used by AP during the boot process.
By then the very first initial context handle is
invalidated because it was already used in the
previous boot cycle by BL1.
BL2 does not need to do this, because the cold
boot starts with BL1.
Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: Id14eefd2ec758f89f672af176e4f5386a397fa35
* changes:
feat(rdfremont): add support for measured boot at BL1 and BL2
feat(arm): mock support for CCA NV ctr
feat(rdfremont): fetch attestation key and token from RSE
feat(psa): introduce generic library for CCA attestation
feat(rdfremont): initialize the rse comms driver
feat(rdfremont): helper to initialize rse-comms with AP-RSE MHUv3
fix(rse): include lib-psa to resolve build
feat(neoverse-rd): add MHUv3 channels on third gen multichip platforms
feat(neoverse-rd): add MHUv3 doorbell channels on third gen platforms
feat(rdfremont): initialize GPT on GPC SMMU block
feat(rdfremont): update Root registers page offset for SMMUv3
feat(rdfremont): enable MTE2 if present on the platform
feat(rdfremont): enable SVE for SWD and NS
feat(rdfremont): enable AMU if present on the platform
feat(rdfremont): enable MPAM if present on the platform
feat(rdfremont): add DRAM pas entries in pas table for multichip
feat(rdfremont): add implementation for GPT setup
feat(rdfremont): integrate DTS files for RD-Fremont variants
feat(rdfremont): add support for RD-Fremont-Cfg2
feat(rdfremont): add support for RD-Fremont-Cfg1
feat(rdfremont): add support for RD-Fremont
feat(neoverse-rd): add scope for RD-Fremont variants
feat(neoverse-rd): add multichip pas entries
feat(neoverse-rd): add pas definitions for third gen platforms
feat(neoverse-rd): add DRAM layout for third gen platforms
feat(neoverse-rd): add SRAM layout for third gen platforms
feat(neoverse-rd): add firmware definitions for third gen platforms
feat(neoverse-rd): add RoS definitions for third gen platforms
feat(neoverse-rd): add CSS definitions for third gen platforms
The function is only used in this file and is static, no need to have
plat_ prefix. And as it is used only in case of FWU, when looking in
metadata, add it in the function name.
Suggested-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I925c9c517216cf93bd74308c280c0f22c7734490
Change [1] migrated Cortex-A32 FVP model to the default version used in
the TF-A CI.
[1] https://review.trustedfirmware.org/c/ci/tf-a-ci-scripts/+/29297
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I038087af957d3ee2b289944b4af1a8cffb1ec5ff
Two diagrams in the documentation contained the string "ARM TF", which
is probably a remainder of the older "ARM Trusted Firmware" name.
Replace that with "TF-A", which is now the more widely known name for
Trusted Firmware.
This was done with an image editing program, by just moving the letters
around, as I didn't find any source for that image.
Change-Id: I1fa18341b3aa8fc8c4ecc8988bf4de66e473caa7
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
SCP_BL2 is part of CCA's TCB. The SCP_BL1 is loaded
by RSE. It has already added to the platform
attestation token. SCP_BL2 was missed, so it is
fixed now.
Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: Ic87743564136f03a901c90ff1ec614f5965b9a47
Add the NAND use case in FWU boot. Like the NOR, NAND FWU won't use
a real partition UUID to find the correct FIP, but the UUID from
metadata will correspond with a hardcoded offset in the NAND.
Implement the plat_try_next_boot_source to load
backup partition on specific device.
Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@foss.st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I1dc544c479743d0ca2aace6e8214813d75637f50
Register a try_nand_backup_partitions() handler to plat_try_images_ops
to manage backup partition when booting from NAND devices.
Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@foss.st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ibee082b7b059b9e2ed502b7bbcda7464e5d9e251
In case of load error, platform may need to try another instance, either
from another storage, or from the same storage in case of PSA FWU. On
MTD devices such as NAND, it is required to define backup partitions.
A new function plat_setup_try_img_ops() should be called by platform
code to register handlers (plat_try_images_ops) to manage loading
other images.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Change-Id: Ideaecaf296c0037a26fb4e6680f33e507111378a
The plat_try_next_boot_source() API is not used by any upstream platform
and not used by platforms that asked for this API. It is then removed.
It will be replaced with a more generic interface in next patch.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I298c7acace8c5efb3c66422d8d9280ecd08e5ade
SPM-MM defines AP TZC-400 regions as such:
1: 0xff000000 0xffffffff S
2: 0x80000000 0xfeffffff NS
3: 0x880000000 0xfffffffff NS
4: 0xff600000 0xff60ffff NS
Region 4 (using filter 0) defines the SPM NS shared buffer between
normal world and secure world.
However region 4 overlaps with region 1 (using filter 0) defined as
secure.
It is forbidden to define overlapping regions beyond region 0 for the
same filter. This is reported as a violation in the TZC-400 controller.
With FVP models < 11.25 the error is latent but not reported to the PE
(reason for this behavior is unclear).
With greater FVP model version the error is reported as an asynchronous
external abort (SError exception).
By carving out the SPM NS shared region (with regions as defined below),
the violation is no longer reported and test passed with recent FVP
models:
1: 0x80000000 0xfeffffff NS
2: 0xff000000 0xff5fffff S
3: 0xff600000 0xff60ffff NS
4: 0xff610000 0xffffffff S
5: 0x880000000 0xfffffffff NS
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Idc3370803ad204ac29efeded77305e52e17cc1c1
Fix the activation order of the CSS to prevent a faulty halt, according
to the reference manual (RM0442 Rev 6, Chapter: 10.4.3 Clock security
system CSS) it must be done after selecting the LSE clock via the RTCSRC
field.
For the HSE clock, this can be activated even when HSEON is '0'.
Signed-off-by: Christoph Fritz <chf@fritzc.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Change-Id: Ied01baac1ccc63dcef78bf5f9180bb8628cce2d0
The struct clk_fixed_rate is used nowhere in the code, remove its
definition.
Change-Id: I139ad05a249357da96a996feabd4b1f53e290f2a
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
RTC clock configuration is done now in OPTEE.
Note: The RTC clock source can only be configured once.
TF-A, configuring the RTC clock source will have no effect in OPTEE.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Change-Id: I111ba96b27d0de0c45086ba8ef947dd2e6785672
Those functions are only used on MP1, they should not be in STM32 clock
core. Move them to MP13 driver (they are already in MP15 driver).
Redefine new clk_stm32_rcc_regs_*lock() functions in clock core. This
change avoid sparse warning:
drivers/st/clk/clk-stm32-core.c:46:6: warning: symbol
'stm32mp1_clk_rcc_regs_lock' was not declared. Should it be static?
drivers/st/clk/clk-stm32-core.c:51:6: warning: symbol
'stm32mp1_clk_rcc_regs_unlock' was not declared. Should it be static?
Change-Id: I9f255acaa843e41fc14267c1a8091f93bd029796
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Re-ordering structures to avoid gaps and minimize data.
Reduce type of gate_refcounts[], uint8_t is enough.
Re-ordering structures to avoid gaps and minimize data.
Use an unsigned char to define a clock ops type.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Change-Id: I6b793dc34abdd6ef013609fc0f122da5d1824a34
TF-A BL32 (SP_MIN) is not supported on STM32MP13. Only OP-TEE is used
as BL32. Remove the code under IMAGE_BL32 flag in STM32MP13 driver.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I6cc9f230782c44129b205e66a44cdb4bcb5f95c3
If the oscillator is not present, the gating will fail.
Change-Id: If9119460a4bcd42053537f1975afe5fe1df05752
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
TF-A BL2 always boot at 650MHz using an algorithm to calculate PLL1
settings, without reading DT. Remove the corresponding nodes.
Change-Id: I0003337d8d37df7b2a70a84b5475f4278c4c4669
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Amit Nagal
Manish Pandey
Manish V Badarkhe
Thomas Fossati
Christophe Kerello
Pascal Paillet
Patrick Delaunay
Jean-Philippe Brucker
XiaoDong Huang
Govindraj Raja
Jayanth Dodderi Chidanand
Chris Kay
Madhukar Pappireddy
Tamas Ban
Yann Gautier
Olivier Deprez
Andre Przywara
Yann Gautier
Christoph Fritz
Gabriel Fernandez