MISRA Violation: MISRA-C: 2012 R.10.1
- The operand to the operator does not have an essentially
unsigned type.
Signed-off-by: HariBabu Gattem <haribabu.gattem@amd.com>
Change-Id: I0f974e9d6f63dddfab55d55c952a57645d931e40
Update test CCA Platform token in fvp_plat_attest_token.c to be
up-to-date with RMM spec Beta0.
Change-Id: I0f5e2ac1149eb6f7a93a997682f41d90e109a049
Signed-off-by: Mate Toth-Pal <mate.toth-pal@arm.com>
DDR4 Chip is EOL during redesign of ls1043ardb pd version. The replacement from MT is MT40A1G8SA-062E:R.
New ddr configure is compatible with both pd and old version of ls1043ardb.
Signed-off-by: Chunlei Xu <chunlei.xu@nxp.com>
Change-Id: I714c091a2cf15046438d0723fb55a4410c386ef4
MISRA Violation: MISRA-C:2012 R.4.6
- Using basic numerical type int rather than a typedef
that includes size and signedness information.
Signed-off-by: HariBabu Gattem <haribabu.gattem@amd.com>
Change-Id: I3779f7b6e074e33cb66ace3bef2117029badce1e
RD-N2* variants of Neoverse reference design platforms could be
configured to boot from SRAM or DRAM. Having ARM_BL31_IN_DRAM set to 1
within the common makefile would deter these platforms from having this
flexibility. Remove the default override configuration for
`ARM_BL31_IN_DRAM`.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I8d79969c003a984675cbe705de890b51a1f7f4ea
Update SRAM size for Neoverse reference design platforms from 256KB to
512KB. This is required to place and execute BL31 image from the
on-chip SRAM. Additionally, revise BL31 image size to accommodate
larger BL31 images of multi-chip platforms.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I11c2672a1089f24a9fafcf6555b8e1d52032cfde
It is more suitable to place platform_def.h in mt8188/include.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I35720690ff4f2ca99c9430edb8bbe17edf9aefb9
Add MCUSYS drivers support for MT8188.
Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.com>
Change-Id: I84107702a9fd021c37d2997ad25b321a483a1a66
DFD (Design for Debug) is a debugging tool, which scans flip-flops and
dumps to internal RAM on the WDT reset. After system reboots, those
values could be showed for debugging.
TEST=build pass.
BUG=b:244216434
Signed-off-by: Fengquan Chen <fengquan.chen@mediatek.corp-partner.google.com>
Change-Id: I468036131e941a46bc1ec12d33105146000730d8
DCM means dynamic clock management, and it can dynamically
slow down or gate clocks during CPU or bus idle.
1. Add MCUSYS related DCM drivers.
2. Enable MCUSYS related DCM by default.
Signed-off-by: Garmin Chang <garmin.chang@mediatek.com>
Change-Id: I131354d72bbc190af504e9639bcc85a720e2bb17
To use power manager function more easier, we add some drivers to let
the implementation easier.
Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.com>
Change-Id: Ibc6e1680c4534592ed37de49da39b6667f468ea1
To support more LPM feature, we add more options for build helper.
Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.com>
Change-Id: I17eeedbe0674e321f1891074ba0c72d858841dae
We are not using cold_boot.[c|h] for mt8188, so remove them first.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I721aca37d5fb422f274bb1ab46150e1eddf7c480
We should wrap cold_boot.h with MTK_SIP_KERNEL_BOOT_ENABLE to avoid
build error.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Idfd760fbb7c782d4fc9de674d86a7123e0129c0d
- Removing platform dependencies from libc modules.
- Replacing panicking with actual error handling.
- Debug macros are included indirectly from assert.h. Removing
"platform_def.h" from assert.h and adding "common/debug.h"
where the macros are used.
- Removing hack for fixing PLAT_LOG_LEVEL_ASSERT to 40.
Instead removing assert with expression, as this
does not provide additional information.
Signed-off-by: Claus Pedersen <claustbp@google.com>
Change-Id: Icc201ea7b63c1277e423c1cfd13fd6816c2bc568
QEMU COSIM platform is equivalent to qemu with additional cosim
extensions, so just switching platform_id to QEMU if QEMU_COSIM is
detected.
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I922d10b1605c7f900158fa7fbe82571d3b9d4792
Increase the max possible size of BL33 from 1MB to 2MB.
For example, edk2 is usually bigger than 1MB
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
Change-Id: Idd4762e25e623de145c65f31cf2dfe1fee466a74
Add support for PM EEMI interface for Versal_net. Also use PM
APIs in psci ops. Added TFA_NO_PM flag to disable PM functionality.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: If2b2941c868bc9b0850d7f3adb81eac0e660c149
Add support to send IPI to firmware.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Akshay Belsare <Akshay.Belsare@amd.com>
Change-Id: I8cd54c05b6a726e0d398dfc1cdcc7f4cf09ba725
CAAM provides serial output during initialization, but the serial init
occurs after CAAM. This leads to serial output produced by CAAM init
function to be omitted and not displayed.
Change the order of initialization and call CAAM init after Serial. This
has no impact as Serial does not require CAAM to be initialized upfront.
Fixes: 2502709f60 ("plat: imx8m: Add caam module init on imx8m")
Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Cc: Jacky Bai <ping.bai@nxp.com>
Change-Id: I09c0a5474a1babfb0b53c4455891689ec08b5bdb
Add SMP support for Versal NET via register access.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Akshay Belsare <Akshay.Belsare@amd.com>
Change-Id: I46d73e2cd678ae720b5255722b6b0611c22659e8
New SoC is a78 based with gicv3 and uart over pl011. Communication
interfaces are similar to Versal platform. System starts with Xilinx PLM
firmware which loads TF-A(bl31) to DDR, which is already configured, and
jumps to it. PLM also prepare handoff structure for TF-A with information
what components were load and flags which indicate which EL level SW should
be started.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Akshay Belsare <Akshay.Belsare@amd.com>
Change-Id: I2a16c242a77be6c91be3d198727dc3b9bbb97410
Serial output is missing the EOL marker, which makes the output garbled.
Add EOL to the output, which adds a newline and makes log output
consistent.
Fixes: 77850c96f2 ("feat(plat/imx8m): do not release JR0 to NS if HAB is using it")
Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Cc: Franck LENORMAND <franck.lenormand@nxp.com>
Cc: Jacky Bai <ping.bai@nxp.com>
Change-Id: I58b67f441016122bc9361d7224d310522917eff0
MISRA Violation: MISRA-C:2012 R.4.6
- Using basic numerical type int rather than a typedef
that includes size and signedness information.
Change-Id: Id85e69b29b124052b4a87462ce27fcdfc00c13c9
Signed-off-by: HariBabu Gattem <haribabu.gattem@amd.com>
ProvenCore requires secure SGIs to be handled at S-EL1. This patch
overrides the default ZynqMP configuration to handle them at EL3 in case
ProvenCore SPD is enabled.
Signed-off-by: Jeremie Corbier <jeremie.corbier@provenrun.com>
Signed-off-by: Mélanie Favre <melanie.favre@provenrun.com>
Change-Id: I2e36d2983f82fbb9b7acf7e18791b8ed92811b60
To fix that the response data is returned when the source size ready
is still fit for response data size.
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Id8924137a5c33888e7042e9ab0e0e8c49b4a41ed
Enable the CSS implementation of the warm reset for the rdn2 platform.
In addition to these changes, fix coding style issues that are not
directly related to the code being introduced in this patch.
Change-Id: I75128d8bbcccbc26cf1e904691c7ef71349c622f
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
To initiate a reset or reboot, the nonsecure OS invokes the PSCI
SYSTEM_RESET function from any one core. As per the PSCI specification,
it is the responsibility of firmware to implement the system view of
the reset or reboot operation. For the platforms supported by CSS,
trigger the reset/reboot operation by sending an SGI to rest all CPUs
which are online. The CPUs respond to this interrupt by initiating its
powerdown sequence.
In addition to these changes, fix coding style issues that are not
directly related to the code being introduced in this patch.
Change-Id: I547253ee28ef7eefa78180d016893671a406bbfa
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Add platform specific interrupt handler for handling the reboot of
all CPU's. On shutdown/reboot, only one CPU invoke PSCI and enter into
trusted firmware. The CPU which entered trusted firmware signals the
rest of the cores which are online using SGI to initiate power down
sequence. On receiving the SGI, the handler will power down the
GIC redistributor interface of the respective core, configure the power
control register and power down the CPU by executing wfi.
In addition to these changes, fix coding style issues that are not
directly related to the code being introduced in this patch.
Change-Id: I4917dfdc47be5ce7367bee629486a6344cdd706f
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Add a new function to setup a SGI interrupt that will be used to trigger
a request for per-cpu power down when executing the PSCI SYSTEM_RESET
request. This will be used on CSS platform that require all the CPUs to
execute the CPU specific power down sequence to complete a warm reboot
sequence in which only the CPUs are power cycled.
Change-Id: I80da0f6c3cd0c5c442c82239ba1e1f773821a7f5
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
If primary core is down, then IPI interrupt should be
routed to another core for processing.
Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Change-Id: I01d7c4232a18c0c3b3f3f9ddadfa6ff5bd2f2471
This patch adds two helper functions:
- plat_ic_raise_ns_sgi to raise a NS SGI
- plat_ic_raise_s_el1_sgi to raise a S-EL1 SGI
Signed-off-by: Florian Lugou <florian.lugou@provenrun.com>
Change-Id: I6f262dd1da1d77fec3f850eb74189e726b8e24da
Instead of exclude code for Versal, define only for ZynqMP.
For new platforms this code should be excluded so instead of
excluding for all platform, define only for ZynqMP.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I45798dadc0f374c5794f517f7d0158675a75caa9
Platform specific IPI header inclusion is not required
in common IPI source file. So remove inclusion of the same.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I6686757f00370c6ec42b5ee2c44ea5cd13da70c0
pm_ipi.h needs some definitions from stddef.h so include it.
Currently it is working because required file is included
indirectly due to other includes.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: Ic4a6c469c3152e21eaeb365ba96f3a29f14593bf
Add missing space in one line comment to follow common coding style.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: Idebf8f34bf48444ee20a68ac3e6fd7f5a41bf8b0
%p is already printing value in hex that's why 0x prefix is not needed.
Origin message looks like this
"NOTICE: Can't read DT at 0x0x100000"
and after fixing
"NOTICE: Can't read DT at 0x100000"
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: If83c485a61441f6105d8cbd797f04060dfce2817
Fix some Misra-C violations. The similar fixes were done by commit
eb0d2b1772 ("fix(zynqmp): resolve misra R15.6 warnings") and commit
dd1fe7178b ("fix(zynqmp): resolve misra R14.4 warnings").
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I3ffa92724a09871f7f99c9ac6c326994c165e9bd
GICD reg write must complete before core goes to idle
mode. Achieve this with dsb() barrier instruction in IPI
ISR
Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Change-Id: I5af42ca901567ee5e54a5434ebe3e673a92cb9be
The commit 389594dfa7 ("fix(zynqmp): move bl31 with DEBUG=1 back to OCM")
tried to move address to OCM but address was actually out of OCM and likely
it was typo. Correct default address should be 0xfffe5000. If TF-A size is
bigger please select location DDR which should be fine for DEBUG cases.
Reported-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I055f3a59cdca527f6029fcc2a19d76be35924d24
Update TZ_VERSION macro name to generic macro name and move to
common header file so that it can be used for keystoneb.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@xilinx.com>
Acked-by: Tanmay Shah <tanmay.shah@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: Ic3819eea78b6c7b51ffaa13081026dd191b76125
Only one hardcode interrupt handler is supported as of now.
This is IPI interrupt between APU and PMC processor.
This patch adds infrastructure to register multiple interrupt
handlers. This infrastructure was used and tested for two
interrupts and so, interrupt id and handler container size is
2 which is defined by MAX_INTR_EL3. Interrupt id is not used
as container index due to size constraints. User is expected to
adjust MAX_INTR_EL3 based on how many interrupts are handled in
TF-A
Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Change-Id: Id49d94f6773fbb6874ccf89c0d12572efc7e678e
PM_FEATURE_CHECK is supported only for platform
management API. PM_LOAD_PDI command is not intended
for platform management. This patch removes version
check of PM_LOAD_PDI and adds version check of command
that is used for SGI registartion.
Signed-off-by: Tanmay Shah <tanmay.shah@xilinx.com>
Change-Id: I353163109b639acab73120f405a811770e8831a0
HariBabu Gattem
Mate Toth-Pal
Chunlei Xu
Rohit Mathew
Bo-Chen Chen
Edward-JW Yang
Fengquan Chen
Dawei Chien
Garmin Chang
Allen-KH Cheng
Claus Pedersen
Sai Pavan Boddu
Jassi Brar
Jay Buddhabhatti
Michal Simek
Andrey Zhizhikin
Jeremie Corbier
Sieu Mun Tang
Pranav Madhu
Tanmay Shah
Florian Lugou
Rajan Vaja
Tanmay Shah