Align STM32MP157C-ED1/EV1 boards PLL nodes with what is done
for DK boards.
Change-Id: I91be408ea1d9b0474caf4965175df33792b7e11e
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Set Ethernet source clock on PLL4P. This is required to enable PTP.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Ia64fbb681d3f04f2b90f373c5eb044f5daa2836c
Cleanup the BL2 device tree file by removing the nodes for the devices
that are not used to boot, depending on compilation flags.
In SDMMC boot, the gain for the dtb file is about 2.3kB.
Change-Id: I3ba13e06dd22b52cff96f51db2dac94b532c81ae
Signed-off-by: Yann Gautier <yann.gautier@st.com>
The kilohertz unit abbreviation should read 'kHz' in DDR
settings files of stm32mp15.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ifa363094f58dd943ef78c653c3e470a216739b41
Move the generic part of DDR node in SOC dtsi file.
DDR dtsi files only include the part configured by CubeMX tool.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
Change-Id: I8c211e9782604da32aeaab98d0ef75fb1cd9c58d
This change enables MPMM and adds, to the TC firmware configuration
device tree, the AMU counters representing the "gears" for the
Maximum Power Mitigation Mechanism feature of the Cortex-X2,
Cortex-A710 and Cortex-A510:
- Gear 0: throttle medium and high bandwidth vector and viruses.
- Gear 1: throttle high bandwidth vector and viruses.
- Gear 2: throttle power viruses only.
This ensures these counters are enabled and context-switched as
expected.
Change-Id: I6df6e0fe3a5362861aa967a78ab7c34fc4bb8fc3
Signed-off-by: Chris Kay <chris.kay@arm.com>
This patch make minor modifications to FVP DTS including modifying
the Non-secure memory range when RME is enabled.
Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I6b3650a2abfff10462a8a2d42755e6d764f7b035
Add support for Arm Ethos-N NPU multi-device.
The device tree parsing currently only supports one NPU device with
multiple cores. To be able to support multi-device NPU configurations
this patch adds support for having multiple NPU devices in the device
tree.
To be able to support multiple NPU devices in the SMC API, it has been
changed in an incompatible way so the API version has been bumped.
Signed-off-by: Laurent Carlier <laurent.carlier@arm.com>
Change-Id: Ide279ce949bd06e8939268b9601c267e45f3edc3
BL2 still uses the STM32 header binary format to be loaded from ROM code.
BL32 and BL33 and their respective device tree files are now put together
in a FIP file.
One DTB is created for each BL. To reduce their sizes, 2 new dtsi file are
in charge of removing useless nodes for a given BL. This is done because
BL2 and BL32 share the same device tree files base.
The previous way of booting is still available, the compilation flag
STM32MP_USE_STM32IMAGE has to be set to 1 in the make command. Some files
are duplicated and their names modified with _stm32_ to avoid too much
switches in the code.
Change-Id: I1ffada0af58486d4cf6044511b51e56b52269817
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Add the UUID into the io policies node that are retrieved
by BL2 using stm32mp_fconf_io.c populate function.
Change-Id: I595d5a41a1e0a27fcc02ea2ab5495d9dbf0e6773
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Create all boards fw-config DT files. They all include a generic
stm32mp15-fw-config.dtsi.
Change-Id: Ib9ac8a59e93e01365001b0d11fee41f7c507c08e
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
This renames tc0 platform folder and files to tc, and introduces
TARGET_PLATFORM variable to account for the differences between
TC0 and TC1.
Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I5b4a83f3453afd12542267091b3edab4c139c5cd
"arm,psci" expects the FIDs for cpu-on, cpu-off and cpu-suspend, which
arent present in the device tree, so remove it from psci compatible.
Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: Icd1ce8ec7fd3f270925e4b3d5d0187088ffe4ba5
The MHUv2 driver has been merged upstream, and it has a different
dts format compared to what was previously used. This patch aligns
with the upstream driver.
Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: Ic963c21c1475d301c3a75686718e6e17841831c3
As FF-A driver probes OP-TEE SP dynamically, these entries are no more
required.
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: Ica091722a7fad13e02662b9b2cd11ca1879b9f80
We will maintain the kernel command line here instead of in U-Boot.
Signed-off-by: Anders Dellien <anders.dellien@arm.com>
Change-Id: I6011306cbaf47717c061f542e180005281695516
Fix the mapping of SCMI clock specifiers to the clusters they drive.
Also, add CPU cores to cluster mappings.
Signed-off-by: Anurag Koul <anurag.koul@arm.com>
Change-Id: I230bea5614de4e29b54e1686b31bf01c0b6aa86c
In the comment in the ARM FPGA DT we promise a generous 100 MB initrd,
but actually describe only a size of 20 MB.
As initrds are the most common and easy userland option for the boards,
let's increase the maximum size to the advertised 100 MB, to avoid
unpacking errors when an initrd exceeds the current limit of 20 MB.
Change-Id: If08ba3fabdad27b2c2aff93b18c3f664728b4348
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This allows the the Matterhorn ELP Arm core to operate at its
designated OPP.
Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I7ccef0cfd079d630c3cfe7874590bf42789a1dca
This patch fixes static checks errors reported for missing copyright in
`include/dt-bindings/interrupt-controller/arm-gic.h` and the include
order of header files in `.dts` and `.dtsi` files.
Change-Id: I2baaf2719fd2c84cbcc08a8f0c4440a17a9f24f6
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Signed-off-by: Chris Kay <chris.kay@arm.com>
Seeed Studio’s SoM‐STM32MP157C is a System‐on‐Module that integrates the
STM32MP157C MPU (the 650 MHz dual‐core variant with a GPU and a
cryptographic processor) the STPMIC1A PMIC, 512 MB of DDR3 RAM and a
4 GB eMMC. There are two LEDs as well, one hardwired to the PMIC’s VDD
output, and the other available at the MPU’s port PG3. The SoM can be
plugged into a carrier board using its three 70‑pin connectors.
Seeed Odyssey‐STM32MP157C is the reference carrier board for the SoM in
a Raspberry Pi‐like form factor. It features a WiFi/Bluetooth chip, a
microSD card port and various I/O interfaces.
The device tree is based on the DKx boards. TF‑A was successfully tested
on the board with Buildroot 2021.02 and U-Boot 2021.04.
Signed-off-by: Grzegorz Szymaszek <gszymaszek@short.pl>
Change-Id: I2c9aecc925561e8d338dddbb192d3bb23a533914
The new pins—PA8, PA9, PE5, and PC7—are described in a new pinctrl node
named “sdmmc2-d47-3”, AKA phandle “sdmmc2_d47_pins_d”. These names are
identical to their Linux kernel counterparts (commit
7af08140979a6e7e12b78c93b8625c8d25b084e2).
Signed-off-by: Grzegorz Szymaszek <gszymaszek@short.pl>
Change-Id: Ie6a019f4361790f6b5d4910ce1e7b507a6c6a21a
Some STM32MP1‐based boards, like Seeed Studio’s SoM‐STM32MP157C, have
the SoC connected to the PMIC via I2C2 instead of I2C4 (which is used on
the official ST development boards). This commit brings TF‑A one step
closer to boot on such boards.
The pins used, PH4 and PH5, are described in a new pinctrl node named
“i2c2-0”, AKA phandle “i2c2_pins_a”. These names are identical to their
Linux kernel counterparts (commit
7af08140979a6e7e12b78c93b8625c8d25b084e2).
Signed-off-by: Grzegorz Szymaszek <gszymaszek@short.pl>
Change-Id: Ief6f0a632cfa992dcf3fed95d266ad6a07a96fe0
Some STM32MP1‐based boards, like Seeed Studio’s SoM‐STM32MP157C, have
the SoC connected to the PMIC via I2C2 instead of I2C4 (which is used on
the official ST development boards). This commit brings TF‑A one step
closer to boot on such boards.
Signed-off-by: Grzegorz Szymaszek <gszymaszek@short.pl>
Change-Id: Iec9c80f29ce95496e8f1b079b7a23f1914b74901
The Arm Generic Timer specification mandates that the
interrupt associated with each timer is low level triggered,
see:
Arm Cortex-A76 Core:
"Each timer provides an active-LOW interrupt output to the SoC."
Arm Cortex-A53 MPCore Processor:
"It generates timer events as active-LOW interrupt outputs and
event streams."
The following files in fdts\
fvp-base-gicv3-psci-common.dtsi
fvp-base-gicv3-psci-aarch32-common.dtsi
fvp-base-gicv2-psci-aarch32.dts
fvp-base-gicv2-psci.dts
fvp-foundation-gicv2-psci.dts
fvp-foundation-gicv3-psci.dts
describe interrupt types as edge rising
IRQ_TYPE_EDGE_RISING = 0x01:
interrupts = <1 13 0xff01>,
<1 14 0xff01>,
<1 11 0xff01>,
<1 10 0xff01>;
, see include\dt-bindings\interrupt-controller\arm-gic.h:
which causes Linux to generate the warnings below:
arch_timer: WARNING: Invalid trigger for IRQ5, assuming level low
arch_timer: WARNING: Please fix your firmware
This patch adds GIC_CPU_MASK_RAW macro definition to
include\dt-bindings\interrupt-controller\arm-gic.h,
modifies interrupt type to IRQ_TYPE_LEVEL_LOW and
makes use of type definitions in arm-gic.h.
Change-Id: Iafa2552a9db85a0559c73353f854e2e0066ab2b9
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
By default the Arm Ethos-N NPU will boot up in secure mode. In this mode
the non-secure world cannot access the registers needed to use the NPU.
To still allow the non-secure world to use the NPU, a SiP service has
been added that can delegate non-secure access to the registers needed
to use it.
Only the HW_CONFIG for the Arm Juno platform has been updated to include
the device tree for the NPU and the platform currently only loads the
HW_CONFIG in AArch64 builds.
Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Change-Id: I65dfd864042ed43faae0a259dcf319cbadb5f3d2
To make it possible to use the hw_config device tree for dynamic
configuration in BL31 on the Arm Juno platform. A placeholder hw_config
has been added that is included in the FIP and a Juno specific BL31
setup has been added to populate fconf with the hw_config.
Juno's BL2 setup has been updated to align it with the new behavior
implemented in the Arm FVP platform, where fw_config is passed in arg1
to BL31 instead of soc_fw_config. The BL31 setup is expected to use the
fw_config passed in arg1 to find the hw_config.
Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Change-Id: Ib3570faa6714f92ab8451e8f1e59779dcf19c0b6
The number of ITS have changed from 4 to 1, resulting
in GICR base address change.
Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I28101f0d1faf9f3c58591b642033c3fd49a275e7
This allows Matterhorn cores to operate at their optimal OPPs.
Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I2e1b784da10154a1f1f65dd0e3a39213e7683116
Increase the core count and add respective entries in DTS.
Add Klein assembly file to cpu sources for core initialization.
Add SCMI entries for cores.
Signed-off-by: Avinash Mehta <avinash.mehta@arm.com>
Change-Id: I14dc1d87df6dcc8d560ade833ce1f92507054747
The value of stdout-path is a string and as a result, we can't use a
label as a reference to the serial0 node. This change fixes the
stdout-path property for N1SDP, Morello and TC0 by pointing to the
right alias.
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Change-Id: I3d403389a424569be56327fab4140fec06f96d37
The Linux Automation MC-1 is a SBC built around the Octavo Systems
OSD32MP15x SiP. The SiP features up to 1 GB DDR3 RAM, EEPROM and
PMIC. The board has eMMC and a SD slot for storage.
The SDRAM calibration values are taken as is from the DKx boards, which
seem to be suitable for operation at German room temperature.
This is deemed ok for now, but for use in the field, the SiP will likely
need to have its timings determined in a climate chamber.
Change-Id: I5f43a61930151ae9d1df2ea7d0f6f9697c813ce0
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Add reserved-memory region for OP-TEE and mark as no-map. This memory
region is used by OP-TEE as non-secure shared RAM.
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I5a22999a8c5550024d0f47e848d35924017df245
This patch adds support to enable OP-TEE as S-EL1 SP with SPMC at S-EL2
- create SPMC manifest file with OP-TEE as SP
- add support for ARM_SPMC_MANIFEST_DTS build option
- add optee entry with ffa as method in tc0.dts
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: Ia9b5c22c6f605d3886914bbac8ac45e8365671cb
Specify peripherals accessed by OP-TEE as a Secure Partition
running as a VM managed by the SPMC.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Icf9aae038e2b1b0ce4696f78ff964bfff8a1498c
This is not a standard string that any kernel recognises, nor do any of
the FDTs embedded in kernels specify this, nor does QEMU's virt machine.
Whilst its presence does no harm, it's not a thing code should consult
as a result, and so drop it in order to not cause confusion and risk
incorrect code being written to search for it.
Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com>
Change-Id: Iea3214a23181c54e600cf8f4f12dfc822140c23d
- Reserve 32MB below ARM_AP_TZC_DRAM1_BASE for TC0_TZC_DRAM1
- Add TC0_NS_DRAM1 base and mapping
- Reserve memory region in tc0.dts
Change-Id: If2431f7f68e4255e28c86a0e89637dab7c424a13
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Without this node, the board fails to boot and panics in the function
stm32mp_init_auth().
Change-Id: Ia54924410dac2a8c94dd6e45d7e93977fe7d87e2
Signed-off-by: Yann Gautier <yann.gautier@st.com>
FMC node bindings are modified to add EBI controller node.
FMC driver and associated device tree files are modified
to support these new bindings.
Change-Id: I4bf201e96a1aca20957e0dac3a3b87caadd05bdc
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
The FPGA images used in Arm Ltd. focus on CPU cores, so they share a
common platform, with a minimal set of peripherals (interconnect, GIC,
UART).
This allows to support most platforms with a single devicetree file.
The topology and number of CPU cores differ, but those will added at
runtime, in BL31. Other adjustments (GICR size, SPE node, command line)
are also done at this point.
Add the common devicetree file to TF-A's build system, so it can be
build together with BL31. At runtime, the resulting .dtb file should be
uploaded to the address given with FPGA_PRELOADED_DTB_BASE at build time.
Change-Id: I3206d6131059502ec96896e95329865452c9d83e
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
There is one dtsi file per SoC version:
- STM32MP151: common part for all version, Single Cortex-A7
- STM32MP153: Dual Cortex-A7
- STM32MP157: + GPU and DSI, but not needed for TF-A
The STM32MP15xC include a cryptography peripheral, add it in a dedicated
file.
There are 4 packages available, for which the IOs number change. Have one
file for each package. The 2 packages AB and AD are added.
STM32157A-DK1 and STM32MP157C-DK2 share most of their features, a common
dkx file is then created.
Some reordering is done in other files, and realign with kernel DT files.
The DDR files are generated with our internal tool, no changes in the
registers values.
Change-Id: I9f2ef00306310abe34b94c2f10fc7a77a10493d1
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Yann Gautier
Yann Gautier
Patrick Delaunay
Nicolas Le Bayon
Chris Kay
Usama Arif
Zelalem Aweke
Laurent Carlier
Lionel Debieve
Arunachalam Ganapathy
Anders Dellien
Anurag Koul
Andre Przywara
Alexei Fedorov
Grzegorz Szymaszek
Mikael Olsson
sah01
Avinash Mehta
Nikos Nikoleris
Ahmad Fatoum
Olivier Deprez
Jessica Clarke
Christophe Kerello
Jagadeesh Ujja
Manoj Kumar