Tree:
5561725107
dependabot/npm_and_yarn/word-wrap-1.2.4
dependabot/pip/docs/markdown-it-py-2.2.0
dependabot/pip/requests-2.31.0
dependabot/pip/urllib3-2.0.6
master
arm_cca_v0.1
arm_cca_v0.2
arm_cca_v0.3
for-v0.4-rc0
for-v0.4/05.20
for-v0.4/05.21
for-v0.4/05.22
lts-test
lts-v2.10.1
lts-v2.10.2
lts-v2.10.3
lts-v2.10.4
lts-v2.8-rc0
lts-v2.8.0
lts-v2.8.1
lts-v2.8.10
lts-v2.8.11
lts-v2.8.12
lts-v2.8.13
lts-v2.8.14
lts-v2.8.15
lts-v2.8.16
lts-v2.8.17
lts-v2.8.18
lts-v2.8.2
lts-v2.8.3
lts-v2.8.4
lts-v2.8.5
lts-v2.8.6
lts-v2.8.7
lts-v2.8.8
lts-v2.8.9
sandbox/lts-v2.10.3-20240319T0822
sandbox/lts-v2.10.3-20240319T1236
sandbox/lts-v2.10.3-20240404T0850
sandbox/lts-v2.10.3-20240405T0714
sandbox/lts-v2.10.3-test1
v0.2
v0.3
v0.3-Juno
v0.3-Juno-0.2
v0.3-Juno-0.3
v0.4
v0.4-Juno-0.4
v0.4-Juno-0.4-rc0
v0.4-Juno-0.5
v0.4-Juno-0.5-rc0
v0.4-Juno-0.5-rc1
v0.4-Juno-0.6-rc0
v0.4-Juno-0.6-rc1
v0.4-rc1
v0.4-rc2
v1.0
v1.0-rc0
v1.1
v1.1-Juno-0.1
v1.1-rc0
v1.1-rc1
v1.1-rc2
v1.1-rc3
v1.2
v1.2-rc0
v1.3
v1.3-rc0
v1.3_rc1
v1.3_rc2
v1.4
v1.4-rc0
v1.5
v1.5-rc0
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v2.10-rc1
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v2.2
v2.2-rc0
v2.2-rc1
v2.2-rc2
v2.3
v2.3-rc0
v2.3-rc1
v2.3-rc2
v2.4
v2.4-rc0
v2.4-rc1
v2.4-rc2
v2.5
v2.5-rc0
v2.5-rc1
v2.6
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v2.6-rc1
v2.7
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v2.7-rc1
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v2.8
v2.8-rc0
v2.8.0
v2.9
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v2.9-rc1
v2.9.0
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364 Commits (55617251071c07569d57b4bf9aa9f6bdef50e704)
Author | SHA1 | Message | Date |
---|---|---|---|
Varun Wadekar | 9a9645105b |
Reserve a Video Memory aperture in DRAM memory
This patch adds support to reserve a memory carveout region in the DRAM on Tegra SoCs. The memory controller provides specific registers to specify the aperture's base and size. This aperture can also be changed dynamically in order to re-size the memory available for DRM video playback. In case of the new aperture not overlapping the previous one, the previous aperture has to be cleared before setting up the new one. This means we do not "leak" any video data to the NS world. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> |
10 years ago |
Varun Wadekar | dc7fdad251 |
Boot Trusted OS' on Tegra SoCs
This patch adds support to run a Trusted OS during boot time. The previous stage bootloader passes the entry point information in the 'bl32_ep_info' structure, which is passed over to the SPD. The build system expects the dispatcher to be passed as an input parameter using the 'SPD=<dispatcher>' option. The Tegra docs have also been updated with this information. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> |
10 years ago |
Varun Wadekar | 08438e24e1 |
Support for NVIDIA's Tegra T210 SoCs
T210 is the latest chip in the Tegra family of SoCs from NVIDIA. It is an ARM v8 dual-cluster (A57/A53) SoC, with any one of the clusters being active at a given point in time. This patch adds support to boot the Trusted Firmware on T210 SoCs. The patch also adds support to boot secondary CPUs, enter/exit core power states for all CPUs in the slow/fast clusters. The support to switch between clusters is still not available in this patch and would be available later. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> |
10 years ago |