Tree:
55cf015c20
dependabot/npm_and_yarn/word-wrap-1.2.4
dependabot/pip/docs/markdown-it-py-2.2.0
dependabot/pip/requests-2.31.0
dependabot/pip/urllib3-2.0.6
master
arm_cca_v0.1
arm_cca_v0.2
arm_cca_v0.3
for-v0.4-rc0
for-v0.4/05.20
for-v0.4/05.21
for-v0.4/05.22
lts-test
lts-v2.10.1
lts-v2.10.2
lts-v2.10.3
lts-v2.10.4
lts-v2.8-rc0
lts-v2.8.0
lts-v2.8.1
lts-v2.8.10
lts-v2.8.11
lts-v2.8.12
lts-v2.8.13
lts-v2.8.14
lts-v2.8.15
lts-v2.8.16
lts-v2.8.17
lts-v2.8.18
lts-v2.8.2
lts-v2.8.3
lts-v2.8.4
lts-v2.8.5
lts-v2.8.6
lts-v2.8.7
lts-v2.8.8
lts-v2.8.9
sandbox/lts-v2.10.3-20240319T0822
sandbox/lts-v2.10.3-20240319T1236
sandbox/lts-v2.10.3-20240404T0850
sandbox/lts-v2.10.3-20240405T0714
sandbox/lts-v2.10.3-test1
v0.2
v0.3
v0.3-Juno
v0.3-Juno-0.2
v0.3-Juno-0.3
v0.4
v0.4-Juno-0.4
v0.4-Juno-0.4-rc0
v0.4-Juno-0.5
v0.4-Juno-0.5-rc0
v0.4-Juno-0.5-rc1
v0.4-Juno-0.6-rc0
v0.4-Juno-0.6-rc1
v0.4-rc1
v0.4-rc2
v1.0
v1.0-rc0
v1.1
v1.1-Juno-0.1
v1.1-rc0
v1.1-rc1
v1.1-rc2
v1.1-rc3
v1.2
v1.2-rc0
v1.3
v1.3-rc0
v1.3_rc1
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v1.4
v1.4-rc0
v1.5
v1.5-rc0
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v1.5-rc3
v1.6
v1.6-rc0
v1.6-rc1
v2.0
v2.0-rc0
v2.1
v2.1-rc0
v2.1-rc1
v2.10
v2.10-rc0
v2.10-rc1
v2.10.0
v2.2
v2.2-rc0
v2.2-rc1
v2.2-rc2
v2.3
v2.3-rc0
v2.3-rc1
v2.3-rc2
v2.4
v2.4-rc0
v2.4-rc1
v2.4-rc2
v2.5
v2.5-rc0
v2.5-rc1
v2.6
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v2.7
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v2.7-rc1
v2.7.0
v2.8
v2.8-rc0
v2.8.0
v2.9
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1 Commits (55cf015c20d6c768344338fd1215c729844a985f)
Author | SHA1 | Message | Date |
---|---|---|---|
Siva Durga Prasad Paladugu | f91c3cb1df |
arm64: versal: Add support for new Xilinx Versal ACAPs
Xilinx is introducing Versal, an adaptive compute acceleration platform (ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Scalar Processing Engines, Adaptable Hardware Engines, and Intelligent Engines with leading-edge memory and interfacing technologies to deliver powerful heterogeneous acceleration for any application. The Versal AI Core series has five devices, offering 128 to 400 AI Engines. The series includes dual-core Arm Cortex-A72 application processors, dual-core Arm Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more than 1,900 DSP engines optimized for high-precision floating point with low latency. This patch adds Virtual QEMU platform support for this SoC "versal_virt". Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
6 years ago |