arm-trusted-firmware

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Author	SHA1	Message	Date
johpow01	7f304b02a8	fix(errata): workaround for Cortex-A510 erratum 2250311 Cortex-A510 erratum 2250311 is a Cat B erratum that applies to revisions r0p0, r0p1, r0p2, r0p3 and r1p0 and is fixed in r1p1. This erratum workaround is a bit different because it interacts with a feature supported in TFA. The typical method of implementing an errata workaround will not work in this case as the MPMM feature would just be re-enabled by context management at every core power on after being disabled by the errata framework. So in addition to disabling MPMM, this workaround also sets a flag in the MPMM runtime framework indicating that the feature should not be enabled even if ENABLE_MPMM=1. SDEN can be found here: https://developer.arm.com/documentation/SDEN2397239 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I7805756e65ec90b6ef8af47e200617c9e07a3a7e	3 years ago
Chris Kay	68120783d6	feat(mpmm): add support for MPMM MPMM - the Maximum Power Mitigation Mechanism - is an optional microarchitectural feature present on some Armv9-A cores, introduced with the Cortex-X2, Cortex-A710 and Cortex-A510 cores. MPMM allows the SoC firmware to detect and limit high activity events to assist in SoC processor power domain dynamic power budgeting and limit the triggering of whole-rail (i.e. clock chopping) responses to overcurrent conditions. This feature is enabled via the `ENABLE_MPMM` build option. Configuration can be done via FCONF by enabling `ENABLE_MPMM_FCONF`, or by via the plaform-implemented `plat_mpmm_topology` function. Change-Id: I77da82808ad4744ece8263f0bf215c5a091c3167 Signed-off-by: Chris Kay <chris.kay@arm.com>	4 years ago

Author

SHA1

Message

Date

johpow01

7f304b02a8

fix(errata): workaround for Cortex-A510 erratum 2250311

Cortex-A510 erratum 2250311 is a Cat B erratum that applies to revisions
r0p0, r0p1, r0p2, r0p3 and r1p0 and is fixed in r1p1.

This erratum workaround is a bit different because it interacts with a
feature supported in TFA. The typical method of implementing an errata
workaround will not work in this case as the MPMM feature would just be
re-enabled by context management at every core power on after being
disabled by the errata framework. So in addition to disabling MPMM, this
workaround also sets a flag in the MPMM runtime framework indicating
that the feature should not be enabled even if ENABLE_MPMM=1.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN2397239

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I7805756e65ec90b6ef8af47e200617c9e07a3a7e

3 years ago

Chris Kay

68120783d6

feat(mpmm): add support for MPMM

MPMM - the Maximum Power Mitigation Mechanism - is an optional
microarchitectural feature present on some Armv9-A cores, introduced
with the Cortex-X2, Cortex-A710 and Cortex-A510 cores.

MPMM allows the SoC firmware to detect and limit high activity events
to assist in SoC processor power domain dynamic power budgeting and
limit the triggering of whole-rail (i.e. clock chopping) responses to
overcurrent conditions.

This feature is enabled via the `ENABLE_MPMM` build option.
Configuration can be done via FCONF by enabling `ENABLE_MPMM_FCONF`, or
by via the plaform-implemented `plat_mpmm_topology` function.

Change-Id: I77da82808ad4744ece8263f0bf215c5a091c3167
Signed-off-by: Chris Kay <chris.kay@arm.com>

4 years ago

2 Commits (5a65fcd5f9c67baa681f664e4596760ca1f2606a)