This patch locks and unlocks access to the S-EL0 SP context when its
runtime state and model are updated to avoid issues around concurrent
access to global state.
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: I427657050574c189cbaf82c1371e3ee44bc1663e
Add the support to parse SP manifest to get device regions, create xlat
table entries for the SP.
SP running at SEL-0 does not have enough privilege to map the regions
itself.
Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: I600f51ee62a33443fe7f1c4e007cc6c5ab45222f
Add the support to parse SP manifest to get memory regions, create xlat
tables and then program it in TTBR0.
SP manifest contains the info on memory map regions that are needed by
the SP. These regions needs to be mapped as SP running at S-EL0 does not
have privilege to do it.
Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: I0cad36e5c43f8a68c94887ff2bd798933a26be27
Secure partition running at SEL0 does not have privilege to modify
translation tables. So it needs SPMC to map the regions for it. Add the
support to request memory map or region info using FF-A interface.
Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Change-Id: I04a97899808bbd45eda24edf7bc74eaef96fb2ce
Add support to setup S-EL0 context by setting up the following
S-EL1 shim exception handlers: This is a trampoline between S-EL0 and
monitor running at EL3 and is used to
handle or forward exceptions from S-EL0.
Boot Info region: This region holds the boot protocol data that is
passed between SPMC and SP.
Setup system registers: Setup sctlr_el1, vbar_el1, cntkctl_el1,
ctx_cpacr_el1(enable fp and smid), spsr and
sp_el0
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: I82d21fcd95529f235bee8bf838d36a2ac519bb0a
The DSU contains system control registers in the SCU and L3 logic to
control the functionality of the cluster. If "DIRECT CONNECT" L3 memory
system variant is used, there won't be any L3 cache, snoop filter, and
SCU logic present hence no system control register will be present.
Hence check SCU presence before accessing DSU register for DSU_2313941
errata.
(commit message taken from commit
942013e1dd by Pramod Kumar
<pramod.kumar@broadcom.com> just errata number changed)
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I38cee6085d6e49ba23de95b3de08bc98798ab2b3
Added changelog for v2.10 release.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
Change-Id: Id06263047fcc1ec60e82f85cd09e2e4bc95830f5
This patch enables support for the gcc compiler option "-mharden-sls",
the default is not to use this option. Setting HARDEN_SLS=1 sets
"-mharden-sls=all" that enables all hardening against straight line
speculation.
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I59f5963c22431571f5aebe7e0c5642b32362f4c9
This reverts commit 0abbfab320.
Reason for revert: Changelog was based on rc0 tag but we got few more patches after that which were not captured.
Change-Id: I9829f2b6dc09f0bd5c538845cbae051f6e4c8a75
Reduce the size of the CPER buffer as it is overlapping with SP's heap
region.
Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: Iaea75a1ffb50ecf0223594fe8bffcebc16da7eab
With SPMC at el3 enabled on rdn2cfg2 configuration BL31 needs more
memory region to accommodate increased xlat table size.
Increase the size by 16K.
Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: Ib235fe35d53a9b85a5ce0a29f2ec4cc3bd85ded9
Cortex-A78C erratum 2743232 is a Cat B erratum that applies
to revisions r0p1 and r0p2 and is still open.
The workaround is to set CPUACTLR5_EL1[56:55] to 2'b01.
SDEN Documentation:
https://developer.arm.com/documentation/SDEN-2004089/latest
Change-Id: Ic62579c2dd69b7a8cbbeaa936f45b2cc9436439a
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
Neoverse V1 erratum 2348377 is a Cat B erratum that applies to
all revisions <= r1p1 and is fixed in r1p2. The workaround is to
set CPUACTLR5_EL1[61] to 1.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1401781/latest
Change-Id: Ica402494f78811c85e56a262e1f60b09915168fe
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
Cortex-X3 erratum 2779509 is a Cat B erratum that applies to
all revisions <= r1p1 and is fixed in r1p2. The workaround is
to set chicken bit CPUACTLR3_EL1[47], this might have a small
impact on power and has negligible impact on performance.
SDEN documentation:
https://developer.arm.com/documentation/2055130/latest
Change-Id: Id92dbae6f1f313b133ffaa018fbf9c078da55d75
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
Arm has made the strategic decision to deprecate the TC1 platform.
Consequently, software development and the creation of fast models
for the TC1 platform have been officially discontinued.
The TC1 platform, now considered obsolete, has been succeeded by
the TC2 platform. It's noteworthy that the TC2 platform is already
integrated and supported in both TF-A and CI repositories.
Change-Id: Ia196a5fc975b4dbf3c913333daf595199968d95d
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
A number of features are marked experimental in the build system through
makefiles but there wasn't an explicit document to list them.
Added a dedicated experimental build options section and moved
existing experimental build option descriptions in this section.
Restoring the change from [1] removing the experimental flag on the EL3
SPMC (this has been lost in rebasing a later change).
[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/24713
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I2c458c6857c347114b265404e8b9ede9ac588463
Currently MediaTek platform code does not support the bl32 image.
Remove bl32 support from Makefile to prevent the build failure when
NEED_BL32 build flag is enabled.
Change-Id: Id8d5663ea5c537390f8ff3ccb427a3a63266545e
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
As part of the release process, revisit the list of maintainers to
keep it updated.
Change-Id: Ifdbbe0d0dd1c8db3e5fbc84affcceb6d3c7716d4
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
This change updates the model versions that we claim to be testing with
to reflect what the reality in the CI.
Change-Id: Ieb44f3f21cd0ba7149d47f7688698831c9eab487
Signed-off-by: Chris Kay <chris.kay@arm.com>
We have to handle wide selection of cpu cores in one TF-A binary:
- v8.0: a53, a57, a72
- v8.2: a55, a76, n1
- v8.4: v1
- v9.0: a710, n2
And then we have QEMU's hybrid: 'max' which has everything QEMU can
emulate.
TF-A for QEMU platforms was built for v8.5 architecture. But turned out
that 'max' has v8.7 flag now (HCX) which we need to have. And this
enabled set of mandatory features which made TF-A not-bootable on
v8.0/8.2 cpus.
So I decided to follow Arm FVP way and do build for v8.0 with set of
feature flags enabled. This way we have bare minimum to make v8.0 cpus
boot. And then all features from newer cores are enabled with runtime
check which makes them boot.
Tested with BSA/SBSA ACS and Debian Linux 6.5 kernel.
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: Ib87bdab992536c65ce0747ce1520682eafc18d39
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Nishant Sharma
Olivier Deprez
Mark Dykes
Manish Pandey
Bipin Ravi
Diederik de Haas
Marcin Juszkiewicz
Manish V Badarkhe
Sandrine Bailleux
Sona Mathew
Juan Pablo Conde
Hsin-Hsiung Wang
Chris Kay
Harrison Mutai
Joanna Farley