The FMU is part of the GIC Distributor (GICD) component. It implements
the following functionality in GIC-600AE:
* Provides software the means to enable or disable a Safety Mechanism
within a GIC block.
* Receives error signaling from all Safety Mechanisms within other GIC
blocks.
* Maintains error records for each GIC block, for software inspection
and provides information on the source of the error.
* Retains error records across functional reset.
* Enables software error recovery testing by providing error injection
capabilities in a Safety Mechanism.
This patch introduces support to enable error detection for all safety
mechanisms provided by the FMU. Platforms are expected to invoke the
initialization function during cold boot.
The support for the FMU is guarded by the GICV3_SUPPORT_GIC600AE_FMU
makefile variable. The default value of this variable is '0'.
Change-Id: I421c3d059624ddefd174cb1140a2d2a2296be0c6
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Up until now we relied on the GICs used in our FPGA images to be GICv3
compliant, without the "direct virtual injection" feature (aka GICv4)
enabled.
To support newer images which have GICv4 compliant GICs, enable the
newly introduced GICv4 detection code, and use that also when we adjust
the redistributor region size in the devicetree.
This allows the same BL31 image to be used with GICv3 or GICv4 FPGA
images.
Change-Id: I9f6435a6d5150983625efe3650a8b7d1ef11b1d1
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
At the moment we have a GIC_ENABLE_V4_EXTN build time variable to
determine whether the GIC interrupt controller is compliant to version
4.0 of the spec or not. This just changes the number of 64K MMIO pages
we expect per redistributor.
To support firmware builds which run on variable systems (emulators,
fast model or FPGAs), let's make this decision at runtime.
The GIC specification provides several architected flags to learn the
size of the MMIO frame per redistributor, we use GICR_TYPER[VLPI] here.
Provide a (static inline) function to return the size of each
redistributor.
We keep the GIC_ENABLE_V4_EXTN build time variable around, but change
its meaning to enable this autodetection code. Systems not defining this
rely on a "pure" GICv3 (as before), but platforms setting it to "1" can
now deal with both configurations.
Change-Id: I9ede4acf058846157a0a9e2ef6103bf07c7655d9
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
At the moment we have a GIC_ENABLE_V4_EXTN build time variable to
determine whether the GIC interrupt controller is compliant to version
4.0 of the GIC spec or not.
In case of the GIC-600 multichip support we were somewhat abusing that
flag to differentiate between a GIC-700 and GIC-600 implementation
being used in the system.
To avoid a build time dependency on this flag, look at the GICD_IIDR
register and check if the hardware is a GIC-600 or not, to make this
decision at runtime. We then use the values for either GIC-700 or the
GIC-600, respectively.
Change-Id: I8c09ec1cd6fd60d28da879ed55ffef5506f9869d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
For the GIC power management we need to identify certain GIC
implementations, so we have the IIDR values for some Arm Ltd. GIC models
defined.
We will need those number elsewhere very soon, so export them to a
shared header file, to avoid defining them again.
Change-Id: I1b8e2d93d6cea0d066866143c89eef736231134f
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Neoverse-N2 erratum 2002655 is a Cat B erratum present in r0p0 of
the Neoverse-N2 processor core, and it is still open.
Neoverse-N2 SDEN: https://documentation-service.arm.com/static/61098b4e3d73a34b640e32c9?token=
Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I1380418146807527abd97cdd4918265949ba5c01
There is no support for 2.5/3.125G SGMII. This 3.125G SerDes mode is not
SGMII. It is just plain 1000Base-X (as defined in IEEE 802.3z standard)
but upclocked 2.5x. This mode is commonly known under name 2500Base-X.
So remove incorrect SGMII keyword from names and comments and replace it
by more adequate 2500Base-X keyword.
There is no functional change in code, just renaming macros and updating
comments.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: If79aec16cc233f4896aafd75bfbbebb3f172a197
Introduced a build flag 'ENABLE_TRF_FOR_NS' to enable trace filter
control registers access in NS-EL2, or NS-EL1 (when NS-EL2 is
implemented but unused).
Change-Id: If3f53b8173a5573424b9a405a4bd8c206ffdeb8c
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Trap bits of trace filter control registers access are in
architecturally UNKNOWN state at boot hence
1. Initialized trap bits to one to prohibit trace filter control
registers accesses in lower ELs (EL2, EL1) in all security states
when FEAT_TRF is implemented.
2. These bits are RES0 when FEAT_TRF is not implemented and hence set
it to zero to aligns with the Arm ARM reference recommendation,
that mentions software must writes RES0 bits with all 0s.
Change-Id: I1b7abf2170ece84ee585c91cda32d22b25c0fc34
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Introduced a build flag 'ENABLE_SYS_REG_TRACE_FOR_NS' to enable trace
system registers access in NS-EL2, or NS-EL1 (when NS-EL2 is
implemented but unused).
Change-Id: Idc1acede4186e101758cbf7bed5af7b634d7d18d
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Trap bits of trace system registers access are in architecturally
UNKNOWN state at boot hence
1. Initialized trap bits to one to prohibit trace system registers
accesses in lower ELs (EL2, EL1) in all security states when system
trace registers are implemented.
2. These bits are RES0 in the absence of system trace register support
and hence set it to zero to aligns with the Arm ARM reference
recommendation,that mentions software must writes RES0 bits with
all 0s.
Change-Id: I4b6c15cda882325273492895d72568b29de89ca3
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Introduced a build flag 'ENABLE_TRBE_FOR_NS' to enable trace buffer
control registers access in NS-EL2, or NS-EL1 (when NS-EL2 is
implemented but unused).
Change-Id: I285a672ccd395eebd377714c992bb21062a729cc
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
1. Refined struct soc_info_t definition.
2. Refined get_soc_info function.
3. Fixed some SVR persernality value.
4. Refined API to get cluster numbers and cores per cluster.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I3c20611a523516cc63330dce4c925e6cda1e93c4
This patch adds the necessary files to support
the SolidRun CN913X CEx7 Evaluation Board.
Because the DRAM connectivity and SerDes settings
is shared with the CN913X DB - reuse relevant
board-specific files.
Change-Id: I75a4554a4373953ca3fdf3b04c4a29c2c4f8ea80
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
The common makefile used by every a8k/cn913x platform
(a8k_common.mk) assumed default paths in PLAT_INCLUDES,
BLE/BL31_PORTING_SOURCES. Allow overriding those
variables, in order to avoid code duplication.
It can be helpful in case using multiple board variants
or sharing common settings between different platforms.
Change-Id: Idce603e44ed04d99fb1e3e11a2bb395d552e2bf7
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Cortex-A710 erratum 2081180 is a Cat B erratum present in r0p0, r1p0,
and r2p0 of the Cortex-A710 processor core, and it is still open.
A710 SDEN: https://developer.arm.com/documentation/SDEN1775101/1000
Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I1e8c2bc3d8dc326947ccfd91daf9083d666b2542
Trap bits of trace buffer control registers access are in
architecturally UNKNOWN state at boot hence
1. Initialized these bits to zero to prohibit trace buffer control
registers accesses in lower ELs (EL2, EL1) in all security states
when FEAT_TRBE is implemented
2. Also, these bits are RES0 when FEAT_TRBE is not implemented, and
hence setting it to zero also aligns with the Arm ARM reference
recommendation, that mentions software must writes RES0 bits with
all 0s
Change-Id: If2752fd314881219f232f21d8e172a9c6d341ea1
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
* changes:
feat(plat/allwinner): add R329 support
refactor(plat/allwinner): allow custom BL31 offset
refactor(plat/allwinner): allow new AA64nAA32 position
fix(plat/allwinner): delay after enabling CPU power
Use a unfied API soc_errata() for each platforms,
add print a INFO message for each enabled errata,
so that it will be easy to check which errata is
enabled on current platform.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I5eab3f338db6b46c57cbad475819043fc60ca6d3
Will add more Erratas, some errata can be used for multiple
platforms, so move errata to be common code which can
be share between different platforms.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Ib149b3eac365bdb593331e9f38f0b89d92c9c0d1
Allwinner R329 is a new dual-core Corte-A53 SoC. Add basical TF-A
support for it, to provide a PSCI implementation containing CPU
boot/shutdown and SoC reset.
Change-Id: I0fa37ee9b4a8e0e1137bf7cf7d614b6ca9624bfe
Signed-off-by: Icenowy Zheng <icenowy@sipeed.com>
Not all Allwinner SoCs have the same arrangement to SRAM A2.
Allow to specify a offset at which BL31 will stay in SRAM A2.
Change-Id: I574140ffd704a796fae0a5c2d0976e85c7fcbdf9
Signed-off-by: Icenowy Zheng <icenowy@sipeed.com>
In newer Allwiner SoCs, the AA64nAA32 wires are mapped to a new register
called "General Control Register0" in the manual rather than the
"Cluster 0 Control Register0" in older SoCs.
Now the position of AA64nAA32 (reg and bit offset) is defined in a few
macros instead assumed to be at bit offset 24 of
SUNXI_CPUCFG_CLS_CTRL_REG0.
Change-Id: I933d00b9a914bf7103e3a9dadbc6d7be1a409668
Signed-off-by: Icenowy Zheng <icenowy@sipeed.com>
Adds a 1us delay after enabling power to a CPU core, to prevent
inrush-caused CPU crash before it's up.
Change-Id: I8f4c1b0dc0d1d976b31ddc30efe7a77a1619b1b3
Signed-off-by: Icenowy Zheng <icenowy@sipeed.com>
Add TZC master source id for DMA in the SoC space and for the DMAs
behind the I/O Virtualization block to allow the non-secure transactions
from these DMAs targeting DRAM.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: I77a2947b01b4b49a7c1940f09cf62b7b5257657c
It was enabled in commit 3c7dcdac5c ("marvell/a3700: Prevent SError
accessing PCIe link while it is down") with a workaround for a bug found
in U-Boot and Linux kernel driver pci-aardvark.c (PCIe controller driver
for Armada 37xx SoC) which results in SError interrupt caused by AXI
SLVERR on external access (syndrome 0xbf000002) and immediate kernel
panic.
Now when proper patches are in both U-Boot and Linux kernel projects,
this workaround in TF-A should not have to be enabled by default
anymore as it has unwanted side effects like propagating all external
aborts, including non-fatal/correctable into EL3 and making them as
fatal which cause immediate abort.
Add documentation for HANDLE_EA_EL3_FIRST build option into Marvell
Armada build section.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Ic92b65bf9923505ab682830afb66c2f6cec70491
A3700 plat_ea_handler was introduced into TF-A codebase just because of
bugs in U-Boot and Linux kernel PCIe controller driver pci-aardvark.c.
These bugs were finally fixed in both U-Boot and Linux kernel drivers:
eccbd4ad8ehttps://git.kernel.org/stable/c/f18139966d072dab8e4398c95ce955a9742e04f7
Add all these information into comments, including printing error
message into a3k plat_ea_handler. Also check that abort is really
asynchronous and comes from lower level than EL3.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I46318d221b39773d5e25b3a0221d7738736ffdf1
Cortex-A710 erratum 1987031 is a Cat B erratum present in r0p0, r1p0,
and r2p0 of the Cortex-A710 processor core, and it is still open.
A710 SDEN: https://documentation-service.arm.com/static/61099dc59ebe3a7dbd3a8a88?token=
Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I9bcff306f82328ad5a0f6e9836020d23c07f7179
Cortex-A78 erratum 1952683 is a Cat B erratum present in r0p0 of
the Cortex-A78 processor core, and it was fixed in r1p0.
A78 SDEN : https://developer.arm.com/documentation/SDEN1401784/1400
Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I77b03e695532cb13e8f8d3f00c43d973781ceeb0
As of DEN0077A FF-A v1.1 Beta0 section 5.2, managed exit
support is moved out of messaging-method field and is described in a
separate field.
Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
Change-Id: Icb12d9dc0d10b11c105dc1920e5212b0359af147
The GIC IP formerly known as "GIC Clayton" has been released under the
name of "GIC-700".
Rename occurences of Clayton in comments and macro names to reflect the
official name.
Change-Id: Ie8c55f7da7753127d58c8382b0033c1b486f7909
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Add missing documentation for MSS_SUPPORT and SCP_BL2 build options used
on Marvell platforms.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I852f60569a9a49269ae296c56cc83eb438528bee
clang build breaks when both ENABLE_PAUTH (BRANCH_PROTECTOR=1)
and CRASH_REPORTING (DEBUG=1) options are enabled:
include/lib/el3_runtime/cpu_data.h:135:2: error: redefinition of typedef
'assert_cpu_data_crash_stack_offset_mismatch' is a C11 feature [-Werror,
-Wtypedef-redefinition]
assert_cpu_data_crash_stack_offset_mismatch);
^
include/lib/el3_runtime/cpu_data.h:128:2: note: previous definition is here
assert_cpu_data_crash_stack_offset_mismatch);
^
1 error generated.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I22c8c45a94a64620007979d55412dbb57b11b813
Cortex A78 AE erratum 1941500 is a Cat B erratum that applies
to revisions <= r0p1. It is still open.
This erratum is avoided by by setting CPUECTLR_EL1[8] to 1.
There is a small performance cost (<0.5%) for setting this
bit.
SDEN is available at https://developer.arm.com/documentation/SDEN1707912/0900
Change-Id: I2d72666468b146714a0340ba114ccf0f5165b39c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
Andre Przywara
Madhukar Pappireddy
nayanpatel-arm
Pali Rohár
Manish Pandey
Manish V Badarkhe
Jiafei Pan
Marcin Wojtas
Joanna Farley
Icenowy Zheng
Vijayenthiran Subramaniam
Maksims Svecovs
Olivier Deprez