This patch adds code owners responsible for maintaining source files
related to runtime services functionality in TF-A.
Change-Id: I24fbbfd017f90a4fae2ffbb94c8eb81d0d837f8e
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Few header files are added to the lists tracking code owners of
various modules in TF-A project.
Also remove drivers/nuvoton directory, which does not exist, from the list
of files maintained by the corresponding owners.
Change-Id: Iad7ce5b1430965237004c9e76e972a3469d20c9d
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Few header files are added to the list maintained by SPMD code owners.
Also, added myself as one of the code owners for SPMD module in TF-A.
Change-Id: Ic017cb98013d349702c35837463586d4aae65543
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Few header files are added to the list maintained by EL3 SPMC
code owner.
Also added missing copyright license footer message.
Change-Id: I72afe4c4e1280ef64610a5efe6d1b0e2c9727bb0
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Phabricator wiki is deprecated, remove TF-A links to this website.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I1255a1513524504636b9c914f9dacf3c54063196
With Commit@55aed7d798f3d48d6aa08d58eb46c4cda318bcfb
we have now updated to use mbedtls 3.6.0.
Update document to reflect the same.
Change-Id: I6bd8fcca795373a05bc6beb2e085d24fdd14932f
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Adds driver support to preserve DSU PMU register values over a DSU
power cycle. This driver needs to be enabled by the platforms that
support DSU and also need it's PMU registers to be preserved
Change-Id: I7fc68a3d7d99ee369379aa5cd114fffc763fc0d2
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
This patch adds some documentation for the context management library.
It mainly covers the design at a higher level, with more focus on
the cold boot and warm boot entries as well as the operations
involved during context switch. Further it also includes a section
on feature enablement for individual world contexts.
Change-Id: I77005730f4df7f183f56a2c6dd04f6362e813c07
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
With addition of vendor-specific el3 monitor service calls debugfs and
pmf are moved from arm-sip to vendor-specific el3 range.
Going forward any changes to SMCCC services can be captured from docs
file table.
Use one FID allocated per sub-feature to track changes in sub-feature.
Modify top level version only when we break version probing or
discovery.
Change-Id: I14ceeab79f29ae57a5d7c523147f6ecaa5574f79
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Move pmf support to vendor-specific EL3 Monitor Service Calls. Remove
pmf call count as it's not supported in vendor-specific el3 as per
SMCCC Documentation 1.5:
https://developer.arm.com/documentation/den0028/latest
Add a deprecation notice to inform PMF is moved from arm-sip range to
vendor-specific EL3 range. PMF support from arm-sip range will be
removed and will not available after TF-A 2.12 release.
Change-Id: Ie1e14aa601d4fc3db352cd5621d842017a18e9ec
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Move debugfs to Vendor-Specific EL3 Monitor Service Calls.
Function Identifier for Vendor-Specific EL3 Monitor Service is '7' and
allocated subranges of Function identifiers to different services are:
0x87000000-0x8700FFFF-SMC32: Vendor-Specific EL3 Monitor Service Calls
0xC7000000-0xC700FFFF-SMC64: Vendor-Specific EL3 Monitor Service Calls
Amend Debugfs FID's to use this range and id.
Add a deprecation notice to inform debugfs moved from arm-sip range to
Vendor-Specific EL3 range. Debugfs support from arm-sip range will be
removed and will not be available after TF-A 2.12 release.
Reference to debugfs component level documentation:
https://trustedfirmware-a.readthedocs.io/en/latest/components/debugfs-design.html#overview
Change-Id: I97a50170178f361f70c95ed0049bc4e278de59d7
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Add support for vendor-specific el3 service. SMCCC 1.5 introduces
support for vendor-specific EL3 monitor calls.
SMCCC Documentation reference:
https://developer.arm.com/docs/den0028/latest
Change-Id: Id8bc43842eecdb7a8a2ec7f31a631e88fe4fe0b4
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Add vendor specific el3 function id and update docs for the same.
SMCCC Documentation reference:
https://developer.arm.com/documentation/den0028/latest
Change-Id: Ieeb63608ad74d7b764d7131d8a92ecf10053c50d
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Layout calculation is spread out between core BL1 logic and common
platform code. Relocate these into common platform code so they are
organised logically.
Change-Id: I8b05403e41b800957a0367316cecd373d10bb1a4
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Add Rohit.Mathew@arm.com to the maintainer list for Neoverse Reference
Design platforms.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I1b8a5714e2707162dd973d9a50215d0a6b622eb1
S32G274ARDB2 is a development board to showcase the capabilities of the
S32G2 SoC. It includes 4 ARM Cortex-A53 cores running at 1.0GHz, 4GBs
of DDR, accelerators for automotive networking and many other
peripherals.
The added support is minimal and only includes the BL2 stage, with no
MMU enabled. The FIP is preloaded by the BootROM in SRAM, and BL2 copies
BL31 and BL33 from FIP to their designated addresses.
Change-Id: Iedda23302768ab70d63787117c5f6f3c21eb9842
Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@nxp.com>
Signed-off-by: Dan Nica <dan.nica@nxp.com>
Signed-off-by: Andra-Teodora Ilie <andra.ilie@nxp.com>
Signed-off-by: Bogdan Roman <bogdan-gabriel.roman@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
As RD-N1-Edge is not planned to be deprecated in the upcoming release
cycles, remove it from the deprecated list.
Change-Id: I6af06e7bd162747aab72384185951d218b388ed3
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
As SGI-575 is not planned to be deprecated in the upcoming release
cycles, remove it from the deprecated list.
Change-Id: Ic9171a3e1bec198d9305e75ac5cae4b40498537e
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Now that EARLY_CONSOLE is generic, use it instead of the ST flag.
Remove stm32mp_setup_early_console() calls as it is done in common TF-A
code.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Icac29b62a6267303cb5c679d15847c013ead1d23
This is a generic porting of what was done on ST platforms with flag
STM32MP_EARLY_CONSOLE. It creates the flag and the prototype for
plat_setup_early_console(). This function depends on platform
implementation. This function call is added at the beginning of each BL
image early setup function.
The patch also introduce an extra log macro: EARLY_ERROR. This can
replace ERROR macro in code that will only be executed before the
default console is enabled, and will do nothing when the EARLY_CONSOLE
is not enabled. This can then save some space in memory.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I77bf0a0c4289b4c7df94e4bfb783a938e05bf023
The ordering of the setup guide is quite confusing, primarly because the
min requirements section is overly verbose. Reconcile this information
into a single table, and present the most important information at the
start of the document i.e. how to get the source, and the tools to
compile.
Change-Id: I1c4d708259e152b101c7282dad19e467d6c36519
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Cortex-X4 erratum 2763018 is a Cat B erratum that is present
in revisions r0p0, r0p1 and is fixed in r0p2.
The workaround is to set bit[47] of CPUACTLR3_EL1 register.
Setting this chicken bit might have a small impact on power
and negligible impact on performance.
SDEN documentation:
https://developer.arm.com/documentation/SDEN2432808/latest
Change-Id: Ia188e08c2eb2952923ec72e2a56efdeea836fe1e
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
Add a section under release for capturing and populating
build options that are deprecated and removed.
Various fixes and refactor[1] led to removal of certain MTE
build options so capture this part in build-options docs.
[1]: https://review.trustedfirmware.org/q/topic:%22mte_fixes%22
Change-Id: I74a82f6f73f7f1dceea65a295ad2df60301ad838
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Changes all occurrences of "RSS" and "rss" in the documentation
to "RSE" and "rse".
Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: Ia42078f5faa1db331b1e5a35f01faeaf1afacb5f
Document bindings for TB_FW_CONFIG that are common between platforms.
Since the information this device tree type contains pertains to
firmware specific properties, we do not expect that the document will
cover all uses, nor do we promise backward compatiblity.
Change-Id: I0e850c13b77cc62940ab5020a15bf8e503568ed8
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
The Arm FVP documentation has grown organically over the years. As a
result, it has become a big document, which can be difficult to digest.
Also, the organization of some of the sections does not make sense. In
particular, all "Running on the ... FVP" sections live under a section
named "Booting a preloaded kernel image (Base FVP)". To illustrate this,
here is the current table of contents:
Arm Fixed Virtual Platforms (FVP)
Fixed Virtual Platform (FVP) Support
Arm FVP Platform Specific Build Options
Booting Firmware Update images
Booting an EL3 payload
Booting a preloaded kernel image (Base FVP)
Obtaining the Flattened Device Treesp
Running on the Foundation FVP with reset to BL1 entrypoint
Running on the AEMv8 Base FVP with reset to BL1 entrypoint
Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint
Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint
Running on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint
Running on the AEMv8 Base FVP with reset to BL31 entrypoint
Running on the AEMv8 Base FVP (AArch32) with reset to SP_MIN entrypoint
Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint
Running on the Cortex-A32 Base FVP (AArch32) with reset to SP_MIN entrypoint
This patch breaks down this document in sub-documents, which are now
included from the index file. The table of contents (ToC) reflects the
new documents hierarchy. The depth of the ToC has been reduced to
simplify the index page. Here is what it looks like now:
Arm Fixed Virtual Platforms (FVP)
Fixed Virtual Platform (FVP) Support
Arm FVP Platform Specific Build Options
Running on the Foundation FVP
Running on the AEMv8 Base FVP
Running on the Cortex-A57-A53 Base FVP
Running on the Cortex-A32 Base FVP (AArch32)
Booting Firmware Update images
Booting an EL3 payload
Booting a preloaded kernel image (Base FVP)
Apart from moving information around in separate files, this patch also
makes the following minor changes to the contents:
- Add a brief introduction about FVPs in the index page.
- Change some of the titles names for conciseness.
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Icb650e0ec2c7a86ccd6e7eea4e16a84c41442c96
Since the TC1 platform has been eliminated from the TF-A source code
and CI script repository, updated the deprecation table to remove its
entry.
Change-Id: I93ae03e1f810666e9a6d0c6172a322ff1e960c71
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Cortex-X4 erratum 2740089 is a Cat B erratum that applies to
all revisions <=r0p1 and is fixed in r0p2. The workaround is to
insert a dsb before the isb in the power down sequence.
SDEN documentation:
https://developer.arm.com/documentation/SDEN2432808/latest
Change-Id: I1d0fa4dd383437044a4467591f65a4a8514cabdc
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
There's a typo in the romlib design document when referring to
the generator script. It should be romlib_generator.py instead
of romlib_generate.py so fixed this typo.
Change-Id: I6db7ee66b13c2b0b9d8511da7e0d1b058366281b
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Our code does not preclude the use of versions 1.0.x of OpenSSL.
Instead, we discourage it's use due to security concerns. Update the
documentation to reflect this.
Change-Id: I5c60907337f10b05d5c43b0384247c5d4135db50
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Cortex-A715 erratum 2728106 is a Cat B(rare) erratum that is present
in revision r0p0, r1p0 and r1p1. It is fixed in r1p2.
The workaround is to execute an implementation specific sequence in
the CPU.
SDEN documentation:
https://developer.arm.com/documentation/SDEN2148827/latest
Change-Id: Ic825f9942e7eb13893fdbb44a2090b897758cbc4
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Updating toolchain to the latest production release version
13.2.Rel1 publicly available on:
https://developer.arm.com/downloads/-/arm-gnu-toolchain-downloads
We build TF-A in CI using x86_64 Linux hosted cross toolchains:
---------------------------------------------------------------
* AArch32 bare-metal target (arm-none-eabi)
* AArch64 bare-metal target (aarch64-none-elf)
Change-Id: I9b60728bcb1a48508ccd4fcbe0114b3029509a64
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Our build system extensively uses syntax and tools that are not natively
supported by Windows shells (i.e., CMD.exe and Powershell). This
dependency necessitates a UNIX-compatible build environment. This commit
updates the prerequisites section in our documentation to reflect this.
Change-Id: Ia7e02d7a335e6c88bbaa0394650f1313cdfd6e40
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
This change adds documentation for the console_list and
console_info structures added to the RMM Boot Manifest v0.3.
Signed-off-by: Harry Moulton <harry.moulton@arm.com>
Change-Id: I3a4f9a4f1d34259bc69c0ab497cbfbc268d7a994
Currently both FEAT_MTE and FEAT_MTE_PERM aren't used for enabling
of any feature bits in EL3. So remove both FEAT handling.
All mte regs that are currently context saved/restored are needed
only when FEAT_MTE2 is enabled, so move to usage of FEAT_MTE2 and
remove FEAT_MTE usage.
BREAKING CHANGE: Any platform or downstream code trying to use
SCR_EL3.ATA bit(26) will see failures as this is now moved to be
used only with FEAT_MTE2 with
commit@ef0d0e5478a3f19cbe70a378b9b184036db38fe2
Change-Id: Id01e154156571f7792135639e17dc5c8d0e17cf8
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Rename Neoverse Poseidon to Neoverse V3, make changes
to related build flags, macros, file names etc.
Change-Id: I9e40ba8f80b7390703d543787e6cd2ab6301e891
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
Cortex-A720 erratum 2926083 is a Cat B erratum that is present
in revisions r0p0, r0p1 and is fixed in r0p2. The errata is only
present when SPE (Statistical Profiling Extension) is implemented
and enabled.
The workaround is to set bits[58:57] of the CPUACTLR_EL1 to 'b11
when SPE is "implemented and enabled".
SDEN documentation:
https://developer.arm.com/documentation/SDEN2439421/latest
Change-Id: I30182c3893416af65b55fca9a913cb4512430434
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Cortex-A720 erratum 2940794 is a Cat B erratum that is present
in revision r0p0, r0p1 and is fixed in r0p2.
The workaround is to set bit[37] of the CPUACTLR2_EL1 to 1.
SDEN documentation:
https://developer.arm.com/documentation/SDEN2439421/latest
Change-Id: I1488802e0ec7c16349c9633bb45de4d0e1faa9ad
Signed-off-by: Bipin Ravi <biprav01@u203721.austin.arm.com>
Incorporate a timing side-channel attack into the TF-A generic
threat model. There is no software mitigation measures in TF-A
against this specific type of attack.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I10e53f8ed85a6da32de4fa6a210805f950018102
Recommend OP-TEE as the default BL32 for STMicroelectronics platforms.
SP_MIN is no more supported in STMicroelectronics software [1].
It will then no more receive new features, but should still remain
as it is in the TF-A code.
[1]: https://wiki.st.com/stm32mpu/wiki/STM32_MPU_OpenSTLinux_release_note_-_v5.0.0#TF-A
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ic49338dbba3fdcebcb1e477e6a1dbde32783482b
Due to embedded SRAM used to load BL2 and BL31 or BL32 has a limited
size, only one storage device or serial device flag should be selected
in TF-A build command line for ST platforms.
This is in line with STMicroelectionics recommendation [1] about those
compilation flags.
[1]: https://wiki.st.com/stm32mpu/wiki/How_to_configure_TF-A_BL2#Build_command_details
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I6f6ab17d45d00289989a606d15c143e5710c64ce
Deprecation notice was sent to the community and no objection was
raised, so removing mbedtls 2.x support.
Change-Id: Id3eb98b55692df98aabe6a7c5a5ec910222c8abd
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Bipin Ravi
Madhukar Pappireddy
Olivier Deprez
Govindraj Raja
Arvind Ram Prakash
Jayanth Dodderi Chidanand
Jason Chen
Harrison Mutai
Rohit Mathew
Ghennadi Procopciuc
Yann Gautier
Yann Gautier
Sona Mathew
Tamas Ban
Sandrine Bailleux
Manish V Badarkhe
Harry Moulton
Bipin Ravi
laurenw-arm