use common code definition and remove zynqmp local definition
for prepare_dtb in dtb flows.
Change-Id: I362b90b96852e9afccc8a2e23d3b7f709280fba7
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
presence of multiple return path in prepare_dtb results in misra c
violation 15.5: this return statement is not the final statement
in the compound statement that forms the body of the function.
prepare_dtb is refactored to address the same.
Change-Id: I17ca4314202d6ca8d6fb0c4ea2ed9d31a152371b
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Address an issue where incorrect macro name is being used for
setting the UART buad rate. Updated the code to use the
appropriate macro name, ensuring that baud rate name is proper.
Fixes: 04a483359f ("feat(xilinx): sync macro names")
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: I27dd8b1559beb0cf7b872de037adc95a948ecc2f
If console is not found there is no way where to print information about
it. Currently only cdns/dcc/pl011 uarts are supported that's why remove
the message which none can see anyway.
But keep "else" part with comment to avoid misra c rule 15.7 violation
which is also missing in Versal NET implementation.
Change-Id: I78e3baffd2288d2a4673099bf193f22029912840
Signed-off-by: Michal Simek <michal.simek@amd.com>
There is no reason to have platform specific macros where generic
macros can be used. This is pretty much preparation step for moving
console code to single location where multiple combinations can be
easier to handle.
Change-Id: I4d85ddef29f5870a9ea9590d4d1564469c6eb87e
Signed-off-by: Michal Simek <michal.simek@amd.com>
CONSOLE_FLAG_CRASH should be also setup to get crash logs on
the same console. Both platforms are using crash console
implementation from plat/common/aarch64/crash_console_helpers.S
that's why there is necessary to setup CONSOLE_FLAG_CRASH.
plat_crash_console_putc() implementation is saying:
"int plat_crash_console_putc(char c)
Prints the character on all consoles registered with the console
framework that have CONSOLE_FLAG_CRASH set. Note that this is only
helpful for crashes that occur after the platform intialization code
has registered a console. Platforms using this implementation need to
ensure that all console drivers they use that have the CRASH flag set
support this (i.e. are written in assembly and comply to the register
clobber requirements of plat_crash_console_putc()."
Change-Id: I314cacbcb0bfcc85fe734882e38718f2763cdbf4
Signed-off-by: Michal Simek <michal.simek@amd.com>
Private plat_crash_console_init() has all the setup commented
that's why it was never been tested.
pl011 uart is supposed to be used as crash console and it should be
enought to add CONSOLE_FLAG_CRASH and remove platform specific
implementation and use generic one.
Early console can't be used for early ASM debugging but that's
expected and not required.
Change-Id: I1267fd78c0d6532a0baddbcad8a5b2a7dfc7750b
Signed-off-by: Michal Simek <michal.simek@amd.com>
flush dcache region for dtb so that dtb cache entries are first written
to disk and are invalidated afterwards to avoid presence of any stale
dtb related entry in the dcache.
Change-Id: Ide0ed58f799b35b690ed790c7498ecdc334e02f5
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
mmap dtb region before usage and unmap it after usage.
overall size(text,data,bss) of dtb gets reduced by
16 bytes in normal flow and 80 bytes in ddr flow.
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Change-Id: I411deff57ab141fc2978a2e916aec2d988cb8f9c
The commit f123b91fdd ("fix(versal): fix BLXX memory
limits for user defined values") and commit a80da3899a
("fix(versal-net): fix BLXX memory limits for user defined
values") fixed issue regarding linker alignment section.
But removing -1 logic is not reflected in plat_fdt() memory
reservation code.
That's why remove +1 from prepare_dtb() not to generate a reserved
memory node with bigger size which ends up with reserving more
space than actually requested by a full featured bootloader or OS.
Change-Id: I0a646cee7d5a55157a6eb1b672c2edbe89e6a57f
Signed-off-by: Michal Simek <michal.simek@amd.com>
Memory reservation in dtb will be done only when TF-A runs from
ddr and dtb load address is provided.
Otherwise prepare_dtb will simply return.
Empty definition of prepare_dtb is removed.
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Change-Id: Ie8a3ec51d60a7389831cfe6a112f722777930623
In absence of definition, PLAT_OCM_BASE is always 0
and IS_TFA_IN_OCM(x) always returns true irrespective
of address passed to it. Reasoning is as mentioned in
Refer section 4.2.3 in
https://gcc.gnu.org/onlinedocs/gcc-3.0.2/cpp_4.html
Due to this,functionality for reservation of TF-A DDR memory in
dtb is never executed.
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Change-Id: Iafb6b7c6aec29bba22f8f7a8395f9caf97548157
All pending interrupts should be handled by their interrupt handlers. CPU
cores remain in suspend state if pending interrupts are cleared.
Signed-off-by: Saeed Nowshadi <saeed.nowshadi@amd.com>
Change-Id: Id8ddf36cbcc07484f232c477277c4da106985c8f
The input argument clock_id in pm_api_clock_get_name function is not
validated against the maximum allowed number. This can lead to OOB
access for ext_clocks variable.
Add check in the pm_api_clock_get_name() to validate clock_id against
CLK_MAX.
Signed-off-by: Naman Trivedi Manojbhai <naman.trivedimanojbhai@amd.com>
Change-Id: Ifa0033d2c557efd6a87b40e366560bc3ba8c602b
Make PMC IPI channel for Versal NET as secure so that NS
systems cannot directly access or modify secure systems.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I75ba8796859dcb35644f3e144d7dc5926755ef78
Make PMC IPI channel for Versal as secure so that NS systems
cannot directly access or modify secure systems.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I22148653fa2d27941cb3031ac790892cee0d1796
Add redundant macro call to increase security by making
code glitch immune as security operations might be
called with the IPI command.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I84d84cca258b7cd981f62816c51032341e19095c
Currently security flag is set to SECURE by default and
is changed to NON_SECURE if NS system is detected. In this
case NS system may access secure system if condition check
gets skipped due to glitches.
So, initialize security_flag to NON_SECURE_FLAG and switch
to SECURE_FLAG if the TrustZone bit is detected to be
in more secure state.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I7af54465bd8744ba97a58c02607631ee23619d47
Add common/debug.h and libfdt.h files to the common file
for XILINX_OF_BOARD_DTB_ADDR configuration.
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Change-Id: I577cc018eda34e186e48594a62c54eb55f11bbd3
As per the current code base, PM_CLOCK_SETRATE and PM_CLOCK_GETRATE
APIs are not supported for the runtime operations in the firmware and
the TF-A it is already returning an error when there is any request
to access these APIs. So, just removing the unused code to avoid the
confusion around these APIs.
Also, there is no issue with the backward compatibility as these APIs
were never used since implemented. Hence no need to bump up the
version of the feature check API as well.
Signed-off-by: Ronak Jain <ronak.jain@amd.com>
Change-Id: I444f973e62cd25aae2e7f697d808210b265106ad
In ZynqMP, the function zynqmp_config_setup() is common between bl31
and bl32(TSP). This function initializes IPI configuration and
prints the chip idcode and revision on the console, which is already
done in bl31 and redundant in bl32(TSP).
Remove the legacy code, reading the chip idcode and
revision information through direct register read.
Change-Id: I5da8e75a597ac9c4e1b56346e065d29e2be8787f
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
TSP(bl32) requires secure interrupts to be handled at S-EL1.
Enable the ZynqMP to handle secure interrupts in S-EL1 by setting
GICV2_G0_FOR_EL3 to 0 in case of SPD=tspd build option.
For ZYNQMP_WDT_RESTART build option GICV2_G0_FOR_EL3 needs to be
enabled and thus for ZynqMP GICV2_G0_FOR_EL3 is set to 1 by default.
On GICv2, when GICV2_G0_FOR_EL3 is set to 1, Group 0 interrupts
target EL3. This allows GICv2 platforms to enable features requiring
EL3 interrupt type.
This also means that all GICv2 Group 0 interrupts are delivered
to EL3, and the Secure Payload interrupts needs to be synchronously
handed over to Secure EL1 for handling.
Change-Id: I7eb72c6588ab41730a74ece261050840646de037
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
In tf-a-ci-scripts repo, change commit 8ffa3d571b(ci(static-checks):
correct include order for *.S macro headers) provides a fix related
to header file include order in assembly files. With the above fix,
improper header order in assembly files has been detected.
Reorder the header includes in assembly files as per the update
in tf-a-ci-scripts.
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: I4a4f3c5bb73886dae234160b893470443f1424fc
In commit b9d26cd3c4 ("chore(xilinx): replace fsbl with xbl"),
function and variable names were changed, but the corresponding
function name in the functional documentation comments is not updated.
Update the function and variable names as per the above commit.
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: I7b777c21fe3673d29f809bf923eba38749f2c024
When the TF-A is placed in DDR memory range, the DDR memory range
needs to be explicitly reserved in the default device tree.
A new build time parameter, XILINX_OF_BOARD_DTB_ADDR, is introduced.
The TF-A will reserve the DDR memory only when a valid DTB address
is provided to XILINX_OF_BOARD_DTB_ADDR during build.
Now the user has options, either manually reserve the desired DDR
address range for TF-A in device tree or let TF-A access and modify
the device tree, to reserve the DDR address range, in runtime using
the build parameter.
Change-Id: I45a5d9a8343ea8a19ea014a70023731de94d061a
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
When the TF-A is placed in DDR memory range, the DDR memory range
needs to be explicitly reserved in the default device tree.
A new build time parameter, XILINX_OF_BOARD_DTB_ADDR, is introduced.
The TF-A will reserve the DDR memory only when a valid DTB address
is provided to XILINX_OF_BOARD_DTB_ADDR during build.
Now the user has options, either manually reserve the desired DDR
address range for TF-A in device tree or let TF-A access and modify
the device tree, to reserve the DDR address range, in runtime using
the build parameter.
Change-Id: I4442a90e1cab5a3a115f4eeb8a7e09e247189ff0
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Currently, the peripheral node indexes are incorrect
for Versal NET due to which incorrect node error is
generated and permission to set the device as wakeup
source is failed. Correct Versal NET peripheral node
indexes to fix above issue.
Fixes: 662aafd6475e ("feat(xilinx): add device node indexes")
Change-Id: I4a2d76f375645e13512599a0272d9322ff6fafd3
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Update the Warning message to be more informative
about the warning being printed.
Change-Id: I923dc5dd760908844d5e1ac8542fd1b04c9f0af5
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Versal NET platform supports multiple cpu clusters and the cluster
information for every partition contaning firmware component
is being passed by PLM through handoff parameters to TF-A.
Function implementation for getting cluster value for the firmware
component partition in TF-A and check for the firmware component
being targeted to be executed on Cluster 0.
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Change-Id: I8622699e12b0a9cda83ae46e2ad0a038ca377fda
Use the IPI command GET_HANDOFF_PARAM to get the PLM to TF-A handoff
parameters. The BL32/BL33 information from the handoff parameters will
be used by TF-A.
If no valid PLM to TF-A handoff parameters are available then,
the TF-A will fall back to the build time information or defaults
set in the TF-A for BL32/BL33.
Once the bootmode identification is supported the default configuration
will be done only for JTAG and for all other bootmodes PLM to TF-A
handoff parameters will be used.
Change-Id: Ia2204fe30fea6f32b4e5d2610820217e6ed23e4d
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
The handoff functionality is common between platforms and all
platforms do not use fsbl terminology. Renaming handoff related code
to generic naming.
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: Ic250af927f33c4fecbc2e6bab01b83a6dd2aab52
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
This commit reorders the include files in accordance with the
guidelines provided by Trusted Firmware-A (TF-A).
The include files are rearranged to ensure a consistent and
organized structure in the codebase, facilitating better
readability and maintainability.
https: //trustedfirmware-a.readthedocs.io/en/latest/process/coding-style.html#headers-and-inclusion
https://git.trustedfirmware.org/ci/tf-a-ci-scripts.git/tree/script/static-checks/
For example, to run header check:
/tf-a-ci-scripts/script/static-checks/check-include-order.py --tree ${PWD} > Includefileorder.txt
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: Ia5802722e69859596b94f31ec40755adbf7d865b
For TF-A, there is no format specified for functional documentation.
For AMD-Xilinx platforms, following kernel-doc format for the functional
documentation to make sure AMD-xilinx documentation is align with
actual code.
For example use kernel-doc from linux to call:
<linux>/scripts/kernel-doc -man -v 1 >/dev/null file...
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: Idcc9def408b6c8da35b36f67ef82fc00890e998c
Type cast the build time base and size argument to unsigned integer
and the limit derived from these two as unsigned long to avoid
size overflow issue during build.
For zynqmp platform, calculating the limit without typecasting results
in build error as follows
make -j DEBUG=0 RESET_TO_BL31=1 PLAT=zynqmp \
ZYNQMP_ATF_MEM_BASE=0x70000000 ZYNQMP_ATF_MEM_SIZE=0x10000000 \
XILINX_OF_BOARD_DTB_ADDR=0x100000 bl31
plat/xilinx/zynqmp/include/platform_def.h:51:62:
error: integer overflow in expression of type 'int' results
in '-2147483648' [-Werror=overflow]
51 | # define BL31_LIMIT (ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_SIZE)
Change-Id: Id093a50e748884d4fba65626e94f361f6c23cecc
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
The commit 0ec6c31320 provides irq to device index mapping
which is required to check for IRQs and set peripheral as a
wake source if IRQ is enabled. But in that commit some IRQ
numbers are missed. Because of that, wakeup using some
peripheral interrupts will not work. Add those missing IRQ
numbers.
Fixes: 0ec6c31320 ("feat(versal): replace irq array with switch case")
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: Icbc773050c328be253702e63e7cf8450c7dee133
The commit 8ce2fbffe3 ("fix(zynqmp): fix BLXX memory limits for user
defined values") fixed logic around BL31_LIMIT but didn't update
prepare_dtb() which is also using +1 logic.
Change-Id: Ia6de10d992a552ca9cfa39c14261b0f94cda95ec
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Don't use BL31_LIMIT macro for validation logic directly but clearly
mark BL31_LIMIT as 64bit address to avoid compilation error when
-Werror=logical-op is passed.
Likely caused by ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_SIZE is in 64bit
logic 0x100000000 and compiler handles it as 32bit value. That's why
error is shown.
Use uint64_t variable for limit and also for base.
Here is command line to replicate this issue:
make realclean; make -j PLAT=zynqmp DEBUG=1 RESET_TO_BL31=1 \
SPD=tspd SDEI_SUPPORT=1 ZYNQMP_ATF_MEM_BASE=0xFFFC0000 \
ZYNQMP_ATF_MEM_SIZE=0x00040000 all -Werror=logical-op
Also error which is coming:
plat/xilinx/zynqmp/zynqmp_sdei.c: In function
'arm_validate_ns_entrypoint':
plat/xilinx/zynqmp/zynqmp_sdei.c:19:40: error: logical 'or' of
collectively exhaustive tests is always true [-Werror=logical-op]
19 | return (entrypoint < BL31_BASE ||
entrypoint > BL31_LIMIT) ? 0 : -1;
Change-Id: Ie1f1b4d2cd94b977aebb72786ecace0b062da418
Signed-off-by: Michal Simek <michal.simek@amd.com>
Since the Arm Trusted Firmware(ATF) has been renamed to Trusted
Firmware-A (TF-A), replace all the instances of ATF from code comments,
macros, variables and functions to TF-A.
Change-Id: Iab448d96158612a3effb4e49943f8d6cb43aaad5
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Pack the structure and make id/ver smaller and sorted.
The change saves 400bytes in RODATA section.
Change-Id: I8bcbe8fd589ba193551a0dd2cd19572516252e73
Signed-off-by: Michal Simek <michal.simek@amd.com>
Add support for SMCCC_ARCH_SOC_ID as per SMC Calling Convention for
Versal NET platform.
The SMCC ARCH SOC ID call is used by system software to obtain the SiP
defined SoC identification details.
Change-Id: I6648051c7f5fa27d2f02080209da36ee8d5a9d95
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Add support for SMCCC_ARCH_SOC_ID as per SMC Calling Convention for
Versal platform.
The SMCC ARCH SOC ID call is used by system software to obtain the SiP
defined SoC identification details.
Change-Id: I1466a9ad1bc8dde1cda516ddd3edbaa6a5941237
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Move the macros to common header from platform specific folder, so that
the same macros can be re-used in other platforms.
Change-Id: I355b024f5e870c6fc104598bc571dbaa29503ae2
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Add support for PM API SYS to get the chip ID from the target.
The API calls the IPI command to read the Chip idcode and revision.
Change-Id: Id4d7d812cbf77c5e2fc7785b8afb379214f8dd19
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
When compiling with user defined areas of memory the platform code
calculates the size with (base + size - 1). However, the linker
file aligns section on a page boundary. So having the -1 in
the size calculations leads to an error message looking like this:
bl31.elf section `coherent_ram' will not fit in region `RAM'
aarch64-buildroot-linux-uclibc-ld: region `RAM' overflowed by 1 byte
While at it fix all other occurences of predefined values that were
calculated with -1.
Fixes: 1d333e6909 ("feat(versal-net): add support for Xilinx
Versal NET platform")
Change-Id: I4455f63ee3ad52369f517a7d8d3627faf0b28c0f
Signed-off-by: Michal Simek <michal.simek@amd.com>
When compiling with user defined areas of memory the platform code
calculates the size with (base + size - 1). However, the linker file
aligns section on a page boundary. So having the -1 in the size
calculations leads to an error message looking like this:
bl31.elf section `coherent_ram' will not fit in region `RAM'
aarch64-buildroot-linux-uclibc-ld: region `RAM' overflowed by 1 byte
While at it fix all other occurences of predefined values that were
calculated with -1
Fixes: commit f91c3cb1df ("arm64: versal: Add support for new Xilinx Versal ACAPs")
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Change-Id: Ica1f97867b701e7fcd60ea8ea07d2ae96c485443
When compiling with user defined areas of memory the platform code
calculates the size with (base + size - 1). However, the linker file
aligns section on a page boundary. So having the -1 in the size
calculations leads to an error message looking like this:
bl31.elf section `coherent_ram' will not fit in region `RAM'
aarch64-buildroot-linux-uclibc-ld: region `RAM' overflowed by 1 byte
Commit 9b4ed0af02 ("feat(plat/zynqmp): fix section `coherent_ram' will not fit in region `RAM'")
applied a similar fix, but only in the predefined for BL31LIMIT/BASE.
While at it fix all other occurences of predefined values that were
calculated with -1
Fixes: 01555332fa ("zynqmp: Revise memory configuration options")
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Change-Id: Ic96e36808d01f6bb92e6839cec92fc52320dd3f3
The array type_el3_interrupt_table is defined for MAX_INTR_EL3(128)
elements and only two interrupts - ARM_IRQ_SEC_SGI_7(15), IRQ_TTC3_1(77)
are being handled. Current implementation is consuming 1024 bytes which
can be optimized for the number of interrupts to be handled.
The current array is replaced with the array of struct
zynmp_intr_info_type_el3_t (id and handler as member) and with
maximum number of interrupts to be handled as the size of array
(MAX_INTR_EL3 = 2). User is expected to adjust MAX_INTR_EL3 based on
how many interrupts are handled in TF-A.
With the updated implementation, a reduction of 960 bytes is observed.
Versal and Versal NET are using similar implementation introduced by
commit e497421d7f ("feat(versal): add infrastructure to handle
multiple interrupts") and commit 0654ab7f75 ("feat(versal-net): add
support for platform management").
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: I07aa388d38ac3ff3c0d25decbe0719087b27ee18
Fix buffer calculation logic for Versal and Versal NET to use
LOCAL/REMOTE_ID.
Change-Id: Icf6985a19183cc8e51f3a536130695e00c32c736
Signed-off-by: Michal Simek <michal.simek@amd.com>
Use new macros IPI_LOCAL_ID/IPI_REMOTE_ID to specify source and
destination channels.
Change-Id: I558eebb4d4a83ae0ca9316824f9dba7426adbe3f
Signed-off-by: Michal Simek <michal.simek@amd.com>
Amit Nagal
Prasad Kummari
Michal Simek
Saeed Nowshadi
Naman Trivedi Manojbhai
Jay Buddhabhatti
Akshay Belsare
Ronak Jain
Ilias Apalodimas