RME patch series shown that we can build larger BL1 than we can run:
NOTICE: Booting Trusted Firmware
NOTICE: BL1: v2.9(debug):v2.9.0-736-g08548888a
NOTICE: BL1: Built : 12:10:39, Sep 18 2023
INFO: BL1: RAM 0x3ffee000 - 0x3fffb000
INFO: BL1: Loading BL2
WARNING: Firmware Image Package header check failed.
RME pushed debug build BL1 over 0x8000 in size.
This exposed an error where FIP_BASE (supposed to be at BL1_SIZE offset
from start of flash) was actually 0x8000 and not 0x12000.
Make sure we have space for BL1 by deriving FIP_BASE from it.
Note: this is a breaking change for edk2 FD image generation, which had
similarly hardcoded a 0x8000 offset. These images must be updated in
lock-step.
Change-Id: I8a1a85e82319945a4412c424467d818d5b6e4ecd
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Add support to qemu "neoverse-n2" cpu for "qemu" platform.
This one has 2^48 address space so will be used by both systems.
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I9f0fa23a4934d9464379495225e08adc121325b4
This reverts commit 9cf7f355ce.
Above mentioned commit was writing to cluster power required bit of
CLUSTERPWRDN register, which provides an advisory status to the power
controller.
Bit definition indication:
0 : Cluster power is not required when all cores are powered down
1 : Cluster power is required even when all cores are powered down
RESET value of this bit is 0
The current implementation in TF-A just programs this bit to 0 when
cluster power down is done but it never sets it to 1. Which actully
does not change any behaviour as the value of this bit always remains 0.
Ideally this bit has to be set to 1 when a core powers up (as RESET
value is 0) and set it to 0 for any core power down except if its last
man standing, in that case we need to ensure the target power level
from OS is cluster then we can do set it to 0.
There also are some investigation needs to be done to find that whether
we need a explicit message to power controller for turning cluster OFF
or it will happen automatically.
Considering this needs a bit of analysis as well as a platform to test
it on, revert the changes which impact the programming during cluster
power down and just keep register defnition.
Change-Id: I4c4ebedae7ca9cd081fb1e0605b9d906d77614d9
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
flush dcache region for dtb so that dtb cache entries are first written
to disk and are invalidated afterwards to avoid presence of any stale
dtb related entry in the dcache.
Change-Id: Ide0ed58f799b35b690ed790c7498ecdc334e02f5
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
mmap dtb region before usage and unmap it after usage.
overall size(text,data,bss) of dtb gets reduced by
16 bytes in normal flow and 80 bytes in ddr flow.
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Change-Id: I411deff57ab141fc2978a2e916aec2d988cb8f9c
The XLAT and MMAP table entries are increased as a part of this
patch: 12fe591 , but this is causing failures for some builds,
so conditionally increased the XLAT and MMAP table entries
Change-Id: I31e8c811bebc767d7187e045a35c9db0eef13ae0
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Add support to "cortex-a55" cpu for "qemu" ('virt') platform.
Signed-off-by: Mark-PK Tsai <mark-pk.tsai@mediatek.com>
Change-Id: I2693892be735eda91494b767322935ddb63c9f48
Add support to qemu "cortex-a710" cpu for "qemu" platform.
CPU is supported by qemu/virt only as qemu/sbsa-ref memory starts at
2^40 which is limit for Cortex-A710.
Switched 'qemu' platform to be built as armv8.5 to cover features of
new cpu core.
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I035790eac41b2caf7f13167e53f48c16f0827754
MULTI_CONSOLE_API have been removed long time ago by commit 5b6ebeec9c
("Remove MULTI_CONSOLE_API flag and references to it") that's why remove
references in platform.mk files and also in one rst which is not valid
anymore.
Change-Id: I45f8e7db0a14ce63de62509100d8159b7aca2657
Signed-off-by: Michal Simek <michal.simek@amd.com>
To be able to boot, STM32MPU platforms require the BL2 binary (together
with its DT) to be preceded with an STM32 header. Add the required
files and macro to properly generate this header.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I675de2c5cb733fe9d9e9baf76a941741a06dfac8
Use UART driver and fill helpers for crash console.
Add early console setup in bl2_el3_early_platform_setup().
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ifb39554214dec05dafe4e306f8754e1454cdab61
This new STMicroelectronics SoC is based on a dual Cortex-A35.
For the moment, only BL2 is compiled with the common parts for ST
platforms.
Change-Id: I1bc4e6835dba4230359ea9b26d736791e27258aa
Signed-off-by: Yann Gautier <yann.gautier@st.com>
This file is common for ST platforms, move it to plat/st/common/.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I7cefbc7f857d4ea63320042988c86d28e8a3cc09
Rename PLAT_NB_FIXED_REGS to PLAT_NB_FIXED_REGUS.
This avoids confusion with regulators and registers.
Signed-off-by: Pascal Paillet <p.paillet@st.com>
Change-Id: Idb2de7204fe978ffcdd729e6cbe453e85fd089b5
Those storage macros are common to all STM32MPU chips, move them to
plat/st/common/include/stm32mp_io_storage.h
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Id20ec00ba65edf9ec7a3a89adfda307c954c3cb6
Those specific SDMMC definitions are only used in stm32_sdmmc2.c driver.
Move them there.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Iac7e505e9421aa7630bee8ce6fc2277b98581995
Use read_sctlr_el3() for aarch64 code instead of read_sctlr().
Change-Id: I17b5d1f8cb2918de6ab1d2d56c15cabca0ed43fd
Signed-off-by: Yann Gautier <yann.gautier@st.com>
To have a more generic code, remove the Q from the *QSPI macros.
Change-Id: I2fa94b54054036c2175df3dfddcb76eec1119ad2
Signed-off-by: Yann Gautier <yann.gautier@st.com>
To make room for all image measurements using the
RME+SPM+TBB+MEASURED_BOOT test configuration, the Event Log's maximum
size has been significantly increased.
Change-Id: I0b9948dab893e14677bca0afa07167648a6c2729
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Maximum entries for MMAP and XLAT have been increased in order to
support the configuration SPM+RME, along with MEASURED_BOOT and
TRUSTED_BOARD_BOOT.
Change-Id: Ic0a0aefecb49d7ccc71357c4bd94e7bd2e5f57c4
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Adds a dummy implementation of the plat_mboot_measure_key() function in
BL1 for QEMU platform.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Change-Id: I5923aad962a5e34d657cf49c177e68ed2ea93291
The commit f123b91fdd ("fix(versal): fix BLXX memory
limits for user defined values") and commit a80da3899a
("fix(versal-net): fix BLXX memory limits for user defined
values") fixed issue regarding linker alignment section.
But removing -1 logic is not reflected in plat_fdt() memory
reservation code.
That's why remove +1 from prepare_dtb() not to generate a reserved
memory node with bigger size which ends up with reserving more
space than actually requested by a full featured bootloader or OS.
Change-Id: I0a646cee7d5a55157a6eb1b672c2edbe89e6a57f
Signed-off-by: Michal Simek <michal.simek@amd.com>
move the gpc reg offset, bit define & macro to a separate header
file for code reuse.
This fixes suspend to mem on i.MX8M Plus too, since the register
layout is different there.
Change-Id: Ibec60c3a68ffa8c378de5334577a7b0e463ca875
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Marek Vasut <marex@denx.de> # Upgrade to latest, update commit message
Similar to the FVP and QEMU, the Arm FPGA systems come with different
CPU cores, and gain new features over time.
Add a list of ARMv9.2 features that require TF-A enablement to be usable
from non-secure world. Their existence will be detected at runtime, so
supporting all those features is not required for using the build.
This fixes the Linux kernel booting on a ARMv9.2 FPGA core.
Change-Id: Ie93c32b13ce4f9968081bf38296cd45edad0a928
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Memory reservation in dtb will be done only when TF-A runs from
ddr and dtb load address is provided.
Otherwise prepare_dtb will simply return.
Empty definition of prepare_dtb is removed.
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Change-Id: Ie8a3ec51d60a7389831cfe6a112f722777930623
In absence of definition, PLAT_OCM_BASE is always 0
and IS_TFA_IN_OCM(x) always returns true irrespective
of address passed to it. Reasoning is as mentioned in
Refer section 4.2.3 in
https://gcc.gnu.org/onlinedocs/gcc-3.0.2/cpp_4.html
Due to this,functionality for reservation of TF-A DDR memory in
dtb is never executed.
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Change-Id: Iafb6b7c6aec29bba22f8f7a8395f9caf97548157
In the absence of ROT_KEY option, there is no need to populate
HASH_PREREQUISITES as the build system uses the hash file specified by
ARM_ROTPK_HASH directly.
Change-Id: Ib08f53b182b8446bbc430f2608471c7dfdc0e58c
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Update the memory layout for both BL31 and BL32 FW based on
the 1GB DRAM space of the AST2700 EVB.
Minor:
- Use SZ_xx macro to define size for better readability
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Change-Id: I6d8285bd675321f615bb67cdd27bb4b6cb4c8b16
Adding basic CPU library code to support Nevis CPU
Change-Id: I399cc9b7b2d907b02b76ea2a3e5abb54e28fbf6c
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
Currently 'pauth_helpers.S' is added if pauth is enabled from main
level makefile.
Change-Id: I33800e280daea6dba6d11e2c494101b369cd8a0b
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
If AACRH32_SP is not specified, it causes the DEFAULT_LINKER_SCRIPT
variable to be empty, and then the linker takes the variable following
it as if it was the linker script, which is not one. This patch
addresses that issue by requiring the AARCH32_SP variable to be set
before continuing.
Change-Id: I21db7d5bd86b98faaa1a1cd3f985daa592556a2d
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
The refactor caused many APIs to be regressed due to copy paste changes
so fix them.
Fixes: 6688fd7aec ("refactor(ti): refactor ti_sci_{setup,do}_xfer to allow zero size response")
Change-Id: I03a808fa0bf2cbefbc1c9924bdaf4cfb2ad7f2cb
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Pointer authentication requires CTX_INCLUDE_PAUTH_REGS to be defined.
Change-Id: I4ca95d6d9e619e7a7296a2c3ecb799683bf70575
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
There are some variables to enable/disable options. Let keep them at top
of file.
Change-Id: I108dd814557b6c713aba0d73a52148c766079c8b
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
There is no need to have two "if" checks for same thing one after
another.
FGT, RNG, SVE, SME are aarch64 only flags.
Change-Id: I6e5850211c859dc7a4ccf6bc8dc6a8d600ffe692
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
SPM_MM is not compatible with ENABLE_SVE_FOR_NS and breaks build early:
> Including SPM Management Mode (MM) makefile
> services/std_svc/spm/spm_mm/spm_mm.mk:14: *** "Error: SPM_MM is not compatible with ENABLE_SVE_FOR_NS". Stop.
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: Iabe181647fce00a432ae11dc4599b71619364c24
Handle coherency in one place for AArch64 mode.
Change-Id: Id3678a8f478e5ef731c81c0df30059000e380758
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Enable SVE, SME, RNG, FGT in one place.
qemu gains FGT (needed for 'max' cpu to boot Linux)
qemu_sbsa gains RNG
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I2e8f971ef3e42d9ebe9f20641b288cc8c40f806a
Move BL31 source list into common file.
Change-Id: Iaa27cfd8f87b691728379c87a6ff6331e87951e1
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Move BL1 and BL2 source list into common file.
Change-Id: I8f9a835f6cd1c5d67728a071860173f80f03c84e
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Keep list of supported cpu cores in one place for both platforms.
qemu_sbsa does not handle some of them but with 256MB firmware space it
does not matter.
Change-Id: I5b8f7d18dc903e86e0cc7babbc2fb3f26a1bfdfa
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Move libfdt includes into common file and use definitions from them.
Change-Id: Ic4fe784fdbedcf5e9e3804a633fcac68464f38a6
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Pass "start_idx" to plat_scmi_clock_rates_array.
This parameter is required to obtain the rate table
a second time.
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
Change-Id: I97c6751e7d34c839ced8f22bddc39fb534978cc4
Macro PLAT_ARM_MAX_BL32_SIZE definition is dependent on
JUNO_AARCH32_EL3_RUNTIME=1. When this value is not set and building
for AArch32, the build fails as it cannot find the definition of the
first macro. With this patch, the problem is addressed by producing
an error when the dependency is not set properly.
Change-Id: Ibe4e976bf79892fd26f3b266bd546218f5616825
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
All pending interrupts should be handled by their interrupt handlers. CPU
cores remain in suspend state if pending interrupts are cleared.
Signed-off-by: Saeed Nowshadi <saeed.nowshadi@amd.com>
Change-Id: Id8ddf36cbcc07484f232c477277c4da106985c8f
The input argument clock_id in pm_api_clock_get_name function is not
validated against the maximum allowed number. This can lead to OOB
access for ext_clocks variable.
Add check in the pm_api_clock_get_name() to validate clock_id against
CLK_MAX.
Signed-off-by: Naman Trivedi Manojbhai <naman.trivedimanojbhai@amd.com>
Change-Id: Ifa0033d2c557efd6a87b40e366560bc3ba8c602b
Marcin Juszkiewicz
Manish Pandey
Amit Nagal
Manish V Badarkhe
Gauri Sahnan
Mark-PK Tsai
Michal Simek
Yann Gautier
Pascal Paillet
Yann Gautier
Jens Wiklander
sahil
Jacky Bai
Marek Vasut
Andre Przywara
Chia-Wei Wang
Juan Pablo Conde
Govindraj Raja
Manorit Chawdhry
Margarita Glushkin
XiaoDong Huang
Saeed Nowshadi
Naman Trivedi Manojbhai