TZMP1 protected memory regions have been added in the Juno platform to
store sensitive data for the Arm(R) Ethos(TM)-N NPU
This is enabled when building TF-A with ARM_ETHOSN_NPU_TZMP1.
The NPU uses two protected memory regions:
1) Firmware region to protect the NPU's firmware from being modified
from the non-secure world
2) Data region for sensitive data used by the NPU
Respective memory region can only be accessed with their unique NSAID.
Signed-off-by: Bjorn Engstrom <bjoern.engstroem@arm.com>
Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Signed-off-by: Rob Hughes <robert.hughes@arm.com>
Change-Id: I65200047f10364ca18681ce348a6edb2ffb9b095
For the Arm(R) Ethos(TM)-N NPU Driver to support running inference with
protected memory the TZC must be configured with appropriate regions.
This is controlled in build time by the now added build flag.
The new build flag is only supported with the Arm Juno platform and the
TZC is configured with default memory regions as if TZMP1 wasn't
enabled to facilitate adding the new memory regions later.
Signed-off-by: Bjorn Engstrom <bjoern.engstroem@arm.com>
Signed-off-by: Rob Hughes <robert.hughes@arm.com>
Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Change-Id: I9dc49ac5d091cfbc8c20d7c3ab394a2836438b0f
It is useful to have a single build for the FVP that includes as much
stuff as possible. Such a build allows a single TF-A build to be used on
a wide variety of fvp command lines. Unfortunately, the fvp also has a
(somewhat arbitrary) SRAM limit and enabling a bunch of stuff overruns
what is available.
To workaround this limit, don't enable everything for all
configurations. The offending configuration is when tsp is enabled, so
try to slim the binary down only when building with it.
As this doesn't solve the issue of running out of space for BL31, update
the linker error to give some clue as to what has (likely) caused it
while more permanent fixes are found.
Also add FEAT_RNG to the mix as it got missed in the commotion.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Icb27cc837c2d90ca182693e9b3121b51383d51fd
* changes:
fix(qemu): enable dynamic feature detection of FEAT_SVE for NormalWorld
fix(tc): enable dynamic feature detection of FEAT_SVE for NormalWorld
FEAT_SVE build macro, "ENABLE_SVE_FOR_NS" default value has been updated
to 2, to support its existing behavior of dynamic detection as well as
keep it aligned with the changes concerning STATE=FEAT_STATE_CHECKED(2),
part of Feature Detection procedure.
Change-Id: Iee43e899f19dc9d5eb57c235998758f462a8c397
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Currently, TF-A supports three states for feature flags:
0: FEAT_DISABLED
1: FEAT_STATE_ALWAYS ( for fixed/real platforms)
2: FEAT_STATE_CHECK ( for configurable platforms)
to meet the feature detection requirements dynamically, mainly
targetting configurable/Fixed Virtual platforms.
With this mechanism in place, we are refactoring all the existing
feature flags to the FEAT_STATE_CHECK option(=2), including
FEAT_SVE explicitly for FVPs.
SVE Patch Reference:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/19888/25
This newly introduced change, breaks the existing behaviour especially
for virtual platforms, who have set the ENABLE_SVE_FOR_NS flag to 1.
Moving ahead, we advise the platforms to take the following steps while
enabling the features:
1. If the platform is configurable (virtual), and want to ensure feature
detection happens dynamically at runtime, set the build flags to
FEAT_STATE_CHECK(=2).
2. For real(fixed) platforms, depending on the features supported by the
hardware and platform wants to enable it, platforms could set build
flags to FEAT_STATE_ALWAYS(=1).
(Note: Only the non-secure world enablement related build flags have
been refactored to take the values within 0 to 2. As earlier Secure
world enablement flags will still remain boolean.)
Henceforth, in order to keep it aligned with this tri-state mechanism,
changing the qemu platform default to the now supported dynamic
option(=2), so the right decision can be made by the code at runtime.
Change-Id: Icc95b8b872378b7874d4345b631adfc314e4dada
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Currently, TF-A supports three states for feature flags:
0: FEAT_DISABLED
1: FEAT_STATE_ALWAYS (for fixed/real platforms)
2: FEAT_STATE_CHECK (for configurable platforms)
to meet the feature detection requirements dynamically, mainly
targetting configurable/Fixed Virtual platforms.
With this mechanism in place, we are refactoring all the existing
feature flags to the FEAT_STATE_CHECK option(=2), including
FEAT_SVE explicitly for FVPs.
SVE Patch Reference:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/19888/25
This newly introduced change, breaks the existing behaviour especially
for virtual platforms, who have set the ENABLE_SVE_FOR_NS flag to 1.
Moving ahead, we advise the platforms to take the following steps while
enabling the features:
1. If the platform is configurable (virtual), and want to ensure feature
detection happens dynamically at runtime, set the build flags to
FEAT_STATE_CHECK(=2).
2. For real(fixed) platforms, depending on the features supported by the
hardware and platform wants to enable it, platforms could set build
flags to FEAT_STATE_ALWAYS(=1).
(Note: Only the non-secure world enablement related build flags have
been refactored to take the values within 0 to 2. As earlier Secure
world enablement flags will still remain boolean.)
Henceforth, in order to keep it aligned with this tri-state mechanism,
changing the TC platform default to the now supported dynamic
option(=2), so the right decision can be made by the code at runtime.
Change-Id: I4c1ebeb55a00a7f148fac1573a6694b7c02a0a81
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
When communicating with the system controller over secure proxy we clear
a thread, write our message, then wait for a response. This must not be
interrupted by a different transfer on the same thread. Take a lock
during this sequence to prevent contention.
Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I7789f017fde7180ab6b4ac07458464b967c8e580
Let the compiler choose when to inline. Here this reduces binary size.
Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I68cd0fc3a94c8c94781ca3dc277a1dd4c6f2bd3a
This allows us to use the common xfer setup path even for no-wait
messages. Then factor that out of each no-wait function.
Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: Ib17d3facd293f3fc91dda56b2906121b43250261
Although we do not use these for anything today, they are returned
in this structure and the struct's definition should match.
While here fix a couple comment typos.
Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: Iac4ec999b44e703e600bde93b0eee83753566876
When building the FVP platform with SPMD (which activates the context
switch code), but keeping ARM_ARCH_MINOR to 4 or lower, the assembler
will complain about the SCXTNUM_EL2 system register not being supported
by the "selected processor".
Allow building this combination of options by defining the SCXTNUM_EL2
register via the generic S3_ encoding, so any assembler, with any -march
settings, will generate the access without any warnings.
We do protect accesses to this register by runtime checks, if not
explicitly requested otherwise, so can override the toolchain in this
case.
Change-Id: I0941f4c4dcf541bd968c153b9c3fac61ca23f7ef
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The patch brings preparation steps before powering on APU
(AI processing unit)
Change-Id: Ica01e035153ec6f3af0de6ba2c66b17a064f8c89
Signed-off-by: Chungying Lu <chungying.lu@mediatek.com>
* changes:
refactor(xilinx): move enum to common place
fix(xilinx): fix misra defects
fix(xilinx): remove unnecessary condition
feat(versal): replace irq array with switch case
feat(versal-net): add support for set wakeup source
refactor(versal): move set wake src fn to common place
Add support for runtime detection (ENABLE_SVE_FOR_NS=2), by splitting
sve_supported() into an ID register reading function and a
second function to report the support status. That function considers
both build time settings and runtime information (if needed), and is
used before we do SVE specific setup.
Change the FVP platform default to the now supported dynamic
option (=2), so the right decision can be made by the code at runtime.
Change-Id: I1caaba2216e8e2a651452254944a003607503216
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Add support for runtime detection (ENABLE_SME_FOR_NS=2), by splitting
feat_sme_supported() into an ID register reading function and a
second function to report the support status. That function considers
both build time settings and runtime information (if needed), and is
used before we do SME specific setup.
Change the FVP platform default to the now supported dynamic option
(=2),so the right decision can be made by the code at runtime.
Change-Id: Ida9ccf737db5be20865b84f42b1f9587be0626ab
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
* changes:
feat(sc7280): add support for PSCI_OS_INIT_MODE
feat(fvp): enable support for PSCI OS-initiated mode
feat(psci): update PSCI_FEATURES
feat(psci): add support for OS-initiated mode
feat(psci): add support for PSCI_SET_SUSPEND_MODE
build(psci): add build option for OS-initiated mode
docs(psci): add design proposal for OS-initiated mode
Moved IOCTL enum from ZynqMP to common place so that it can be used
for all the platforms.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I6ad992da30f2def9f46c8ba79753d79ed00fe024
Remove unnecessary condition check from pm_client_set_wakeup_sources()
as the code will never get to this condition.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: Ia046e1188fdf6e024a146d3f4dd3d8f87a285e7f
Replaced array of interrupt to PM node index map with switch-case for
Versal. As a result, the size of code got reduced by 527 bytes. In case
of error return invalid node index i.e. XPM_NODEIDX_DEV_MIN.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: Ifb17366362e2d1757d8933e1ce29083f7ad86b8f
Currently wakeup source is not getting setup during suspend resume.
Add support to set wakeup source as per IRQ enabled using switch-case
instead of static array as it is more efficient.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I30d7ceb3a1d56ba5174fc7334f3a29081c918c92
Moved pm_client_set_wakeup_sources() to make common for both Versal and
Versal NET platforms.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: Ib82c5f85a0a27bc47940f6796f1cf68b2c38a908
Rename macros PLAT_VERSAL_GICD_BASE, PLAT_VERSAL_GICR_BASE,
PLAT_VERSAL_NET_GICD_BASE and PLAT_VERSAL_NET_GICR_BASE to
PLAT_GICD_BASE_VALUE and PLAT_GICR_BASE_VALUE to make common
for both Versal and Versal NET platforms.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: Ibcebfb8e741e828ef272b32cbedfb4dcbf8629b6
Add additional Versal NET device node indexes to the existing list
that are for new APU cores, RPU cores, OCM and TCM memories, USB 1
and WDT devices.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: Iea0570ae5d81de9c5b2793329ae1e7284b6c5a3f
Initialized values explicitly to device enum members to avoid
value assignment from the compiler and for better readability.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I20f24c3b4fb47b2b011def9f1f43ea8238c66b80
Moved pm_defs.h file to common place so that it can be used for
Versal NET and ZynqMP. Also moved common code from zynqmp_pm_defs.h to
common place.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I2ee1e72258c6052cdd6467cdbcf4009afb98da49
Moved necessary files to common place so that it can be used for
Versal NET.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I611fa849207b082e6599acfb65c55d27b9c99435
The AMU extension code was using its own feature detection routines.
Replace them with the generic CPU feature handlers (defined in
arch_features.h), which get updated to cover the v1p1 variant as well.
Change-Id: I8540f1e745d7b02a25a6c6cdf2a39d6f5e21f2aa
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
So far we have the ENABLE_AMU build option to include AMU register
handling code for enabling and context switch. There is also an
ENABLE_FEAT_AMUv1 option, solely to protect the HAFGRTR_EL2 system
register handling. The latter needs some alignment with the new feature
scheme, but it conceptually overlaps with the ENABLE_AMU option.
Since there is no real need for two separate options, unify both into a
new ENABLE_FEAT_AMU name in a first step. This is mostly just renaming at
this point, a subsequent patch will make use of the new feature handling
scheme.
Change-Id: I97d8a55bdee2ed1e1509fa9f2b09fd0bdd82736e
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Build Platform Management(PM) code as an Library.
Building PM code as library provides an option to switch to different
firmware interfaces like custom packages.
Change-Id: I872d45edf55ac83a6efb86591d12a0fef7b598cb
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
The base address for BL32 and BL33 is read from the FSBL to TF-A
handoff params.
Print the base address for BL32 and BL33 as entry to the secure and
non-secure world respectively in the release build.
Change-Id: Icc976fccb56b565f78001d87b02180ced6437a43
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
* changes:
refactor(cpufeat): enable FEAT_RNG for FEAT_STATE_CHECKED
refactor(cpufeat): align FEAT_SEL2 to new feature handling
refactor(cpufeat): enable FEAT_NV2 for FEAT_STATE_CHECKED
refactor(cpufeat): enable FEAT_TWED for FEAT_STATE_CHECKED
refactor(cpufeat): enable FEAT_CSV2_2 for FEAT_STATE_CHECKED
refactor(cpufeat): enable FEAT_ECV for FEAT_STATE_CHECKED
refactor(cpufeat): enable FEAT_PAN for FEAT_STATE_CHECKED
refactor(cpufeat): align FEAT_SB to new feature handling
refactor(cpufeat): use alternative encoding for "SB" barrier
refactor(cpufeat): enable SYS_REG_TRACE for FEAT_STATE_CHECKED
fix(cpufeat): make stub enable functions "static inline"
fix(mpam): feat_detect: support major/minor
Bjorn Engstrom
Joanna Farley
Boyan Karatotev
Manish Pandey
Jayanth Dodderi Chidanand
Madhukar Pappireddy
Andrew Davis
Andre Przywara
Julius Werner
Mark Dykes
Chungying Lu
Jay Buddhabhatti
Amit Nagal
Akshay Belsare
Bo-Chen Chen