This patch enables FEAT_Debugv8p9 and prevents EL1/0 from
trapping to EL3 when accessing MDSELR_EL1 register by
setting the MDCR_EL3.EBWE bit.
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I3613af1dd8cb8c0d3c33dc959f170846c0b9695a
* changes:
feat(nxp-clk): set rate for clock fixed divider
feat(nxp-clk): add A53 clock objects
feat(nxp-clk): set rate for PLL divider objects
feat(nxp-clk): set rate for PLL objects
Add set rate support for fixed divider clock modules of whose role is to
reduce the source frequency by a factor.
Change-Id: I8a29a2c5b1a829db0c396407c3517c9e66caaa93
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
These objects are needed to allow early enablement of the A53 core
clock.
Change-Id: I44d81975c8eba8cc6cfd18aeb6c9b324edaa3f01
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Add implementation for ARM PLL divider rate set mechanism.
Change-Id: I78f4418bcbb5ea0a6ef64675e44bd074d2230ea3
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Add implementation for ARM PLL rate set mechanism.
Change-Id: Ic859567bd67747f173d425158cdc581801f7446c
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
This is a small change to split up the generation of the RZ/G layout
images into unique targets. This is predominantly for cleanliness
reasons - Make current doesn't know about the `.bin` and `.srec`
binaries generated by the `.elf` target.
Change-Id: I81251ac647b85c5eec8f910ddc841a5a32b49e67
Signed-off-by: Chris Kay <chris.kay@arm.com>
This is a small change to split up the generation of the R-Car layout
images into unique targets. This is predominantly for cleanliness
reasons - Make current doesn't know about the `.bin` and `.srec`
binaries generated by the `.elf` target.
Change-Id: I624bc0c62e99cead66a6d6e25ff016aecf6b985a
Signed-off-by: Chris Kay <chris.kay@arm.com>
Arm has decided to rename RD-Fremont to RD-V3 to align with its
existing product lineup, such as RD-V1, RD-V2, etc. This change
replaces all occurences of "Fremont" with "V3" in file names and
contents.
Change-Id: I302103492f962a7ac74854633ad68701b2a7f420
Signed-off-by: Jerry Wang <Jerry.Wang4@arm.com>
Refactor to properly handle the case when the variable has a value
of 'n'.
Change-Id: I2f5045253511ec5e5d717821d8428c4e3ed6b7b6
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
The RSE_CRYPTO_EXPORT_PUBLIC_KEY_SID macro does not match the definition
in RSE. A paired macro, TFM_CRYPTO_EXPORT_PUBLIC_KEY, in the RSE's
header (located in interface/include/tfm_crypto_defs.h) is defined as
0x206. This causes the TF-A test PLATFORM_TEST=rse-rotpk to fail.
Correct the definition of RSE_CRYPTO_EXPORT_PUBLIC_KEY_SID to make the
test pass.
Change-Id: I0bc24ed6dd23f2718e1edea5ec464545dab06983
Signed-off-by: Leo Yan <leo.yan@arm.com>
Fix BL31 crashes caused by incorrect placement of firmware handoff code
within an assert. The function call has been removed from the assert to
ensure it’s executed even when assertions are disabled.
Change-Id: I668f5c08af33327e8ff0e22887c3da109bd6be31
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
In bl2_plat_handle_post_image_load(), if the image_base of OP-TEE
header image is 0, do not call optee_header_is_valid(). This can be
the case when OP-TEE is not present in the FIP.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ic2d014e59665c9efa33bbce1bf2eb3b66cd6fb26
* changes:
build(deps): bump certifi from 2023.7.22 to 2024.7.4
build(deps): bump idna from 3.4 to 3.7
build(deps): bump requests from 2.31.0 to 2.32.2
build(deps): bump jinja2 from 3.1.2 to 3.1.4
build(deps): bump urllib3 from 2.0.2 to 2.2.2
build(deps): bump pip from 23.1.2 to 23.3
By tracing instruction execution, it is observed:
Placing plat_my_core_pos at top of functions translate by the compiler
into calling those functions even if the result is not consumed when not
printed.
plat_my_core_pos is used to retrieve the core id for the currently
running core, but effectively call sites are only consuming it for
verbosity purposes. Move plat_my_core_pos calls into the print functions
that require it.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Ia3549453b5e4de7c575a8887a4d19e318658d03e
As observed by tracing instruction execution the SMC_RET18
macro in spmd_smc_switch_state calls cm_get_context, however the
compiler expands it to multiple individual non-inlined calls to
this same function. Store the result of cm_get_context into a local
variable and use it in the macro such that this function is only called
once.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Ib4fa63aced2f07c67c057f54fef3780c85e91df7
spmd_get_context_by_mpidr calls plat_core_pos_by_mpidr defined in
platform's fvp_topology. This involves a lot of intricated inner calls
including access to power controller (taking/releasing a bakery lock).
Remove dependency from this function, and use plat_my_core_pos instead.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I8e91858922e339de51056dba8803db74c8fd7420
Keeping the MTE2 enablement under the SPMD check is breaking for FPGA
and CI test, as SPMD is absent in these cases.
Enable MTE2 unconditionally so that all the supported platforms can use
it.
Change-Id: Id86893f0e2767a8686c3dca0ea092907d5c107ba
Signed-off-by: Tintu Thomas <tintu.thomas@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
Set the parent for ARM PLL and MC_CGM muxes as part of the early clocks
enablement.
Change-Id: If88186caad520c3f7bb1fb602de526d940037a1c
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
The MC_CGM1 clock objects will participate in A53 clocking.
Change-Id: I7309b630d72ac0ad66df7c299b678454220e0581
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
On S32CC SoCs, the set_parent operation will be used on clock modules
that are mux instances in order to establish the clock source. This will
be used for PLLs and MC_CGM muxes.
Change-Id: I7228d379500ea790459b858da8fc0bdcbed4fd62
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Add all the clock objects needed to describe the ARM PLL, which can be
powered by either FXOSC or FIRC oscillators.
Change-Id: I2585ed38178ca1d5c5485adb38af1b3b8d94f1f6
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Add the low-level implementation to enable the FXOSC oscillator, which
is disabled by default when booting the SoC. It will be used by PLLs,
for which support will be added later.
Change-Id: Ie784e4e29b8b4453b39d37594c311af940bebf92
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Arvind Ram Prakash
Madhukar Pappireddy
Manish V Badarkhe
Manish Pandey
Ghennadi Procopciuc
Chris Kay
Jerry Wang
Hsin-Hsiung Wang
Leo Yan
Harrison Mutai
Olivier Deprez
Yann Gautier
dependabot[bot]
Tintu Thomas