* changes:
feat(plat/fvp): enable trace extension features by default
feat(trf): enable trace filter control register access from lower NS EL
feat(trf): initialize trap settings of trace filter control registers access
feat(sys_reg_trace): enable trace system registers access from lower NS ELs
feat(sys_reg_trace): initialize trap settings of trace system registers access
feat(trbe): enable access to trace buffer control registers from lower NS EL
feat(trbe): initialize trap settings of trace buffer control registers access
Trusted Services had removed secure storage and added two new
trusted services - Protected Storage and Internal Trusted Storage.
Hence we are removing secure storage and adding support for the
internal trusted storage.
And enable external SP images in BL2 config for TC, so that
we do not have to modify this file whenever the list of SPs
changes. It is already implemented for fvp in the below commit.
commit 33993a3737
Author: Balint Dobszay <balint.dobszay@arm.com>
Date: Fri Mar 26 15:19:11 2021 +0100
feat(fvp): enable external SP images in BL2 config
Change-Id: I3e0a0973df3644413ca5c3a32f36d44c8efd49c7
Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
Disabling filter 0 causes inability to access DRAM.
An attempt leads to an abort.
ARM manual disallows to disable filter 0, but if we do
that from SRAM, nothing bad happens.
This patch prevents disabling of a filter 0, allowing to
reconfigure other filters from DRAM.
Note: this patch doesn't change the logic after reset.
It is only needed in case someone wants to reconfigure the
previously configured TZASC.
Change-Id: I196a0cb110a89afbde97f64a94df3101f28708a4
Signed-off-by: stsp@users.sourceforge.net
EMI MPU stands for external memory interface memory protect unit.
MT8195 supports 32 regions and 16 domains.
We add basic drivers currently, and will add more setting for
EMI MPU in next patch.
Change-Id: Iedc19d8f6fcf1ceb2d8241319b8dc17c885642dd
Signed-off-by: Penny Jan <penny.jan@mediatek.com>
In the SCMI power domain off handling, configure GIC
to prevent interrupt toward to the core to be turned off,
and configure CCN to disable coherency when the cluster is turned off.
The same operation is done in SCPI power domain off processing.
This commit adds the missing operation in SCMI power domain
off handling.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Change-Id: Ib3523de488500c2e8bdc74e4cb8772a1442d9781
This patch will fix the formatting errors concerning code snippet,
lines 245 and 256 respectively.
The code snippet is updated to 'shell' to lex it appropriately.
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: I53aefd81da350b6511e7a97b5fee7b0d6f9dde2d
Erratum 1530924 affects Armada 37xx CPU, since it affects all Cortex-A53
revisions from r0p0 to r0p4.
Enable the workaround for this erratum.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I753225040e49e956788d5617cd7ce76d5e6ea8e8
Describe the boot using FIP, and how to compile it.
The STM32IMAGE boot chain is still available but it is not recommended.
Update the build command lines, for FIP.
The memory mapping is also updated.
Change-Id: I2b1e0df5500b6213d33dc558b0e0da38340a4d79
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Add a new function that allows to enable or disabled filters on
configured regions dynamically. This will avoid the need to
reconfigure the entire attribute and just manage to
enable/disable filters.
Change-Id: If0937ca755bec6c45d3649718147108459682fff
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Added a sub-section in the "Processes and Policies" chapter under
Contributor's guide on how to add new build configurations when new
source files are added to the TF-A repository. This will help the patch
contributor to update their files to get analysed by Coverity Scan.
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: I71f410a061028f89bd0e984e48e61e5935616d71
BL2 passes FW_CONFIG to BL31 which contains information
about different DTBs present. BL31 then uses FW_CONFIG
to get the base address of HW_CONFIG and populate fconf.
Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I0b4fc83e6e0a0b9401f692516654eb9a3b037616
This avoids duplicate define of TZC_REGION_NSEC_ALL_ACCESS_RDWR.
And remove the previous TZC400 definitions from stm32mp1_def.h.
Change-Id: I6c72c2a18731f69d855fbce8ce822a21da9364fa
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Add required code to support FCONF on STM32MP1 platform.
The new FW_CONFIG DT file will be inside the FIP, and loaded by BL2.
It will be used to configure the addresses where to load other binaries.
BL2 should be agnostic of which BL32 is in the FIP (OP-TEE or SP_min),
so optee_utils.c is always compiled, and some OP-TEE flags are removed.
Change-Id: Id957b49b0117864136250bfc416664f815043ada
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Instead of using a scratch buffer of 512 bytes, we can directly use the
image address and max size. The mmc_block_dev_spec struct info is then
overwritten for each image with this info, except FW_CONFIG and GPT
table which will still use the scratch buffer.
This allows using multiple blocks read on MMC, and so improves the boot
time.
A cache invalidate is required for the remaining data not used from the
first and last blocks read. It is not required for FW_CONFIG_ID,
as it is in scratch buffer in SYSRAM, and also because bl_mem_params
struct is overwritten in this case. This should also not be done if
the image is not found (OP-TEE extra binaries when using SP_min).
Change-Id: If3ecfdfe35bb9db66284036ca49c4bd1be4fd121
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
BL2 still uses the STM32 header binary format to be loaded from ROM code.
BL32 and BL33 and their respective device tree files are now put together
in a FIP file.
One DTB is created for each BL. To reduce their sizes, 2 new dtsi file are
in charge of removing useless nodes for a given BL. This is done because
BL2 and BL32 share the same device tree files base.
The previous way of booting is still available, the compilation flag
STM32MP_USE_STM32IMAGE has to be set to 1 in the make command. Some files
are duplicated and their names modified with _stm32_ to avoid too much
switches in the code.
Change-Id: I1ffada0af58486d4cf6044511b51e56b52269817
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Add bindings that will be used to define DDR regions
and their access rights.
Change-Id: I745a7e580ef2b9e251d53db12c5a0a86dfe34463
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Add the UUID into the io policies node that are retrieved
by BL2 using stm32mp_fconf_io.c populate function.
Change-Id: I595d5a41a1e0a27fcc02ea2ab5495d9dbf0e6773
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Create all boards fw-config DT files. They all include a generic
stm32mp15-fw-config.dtsi.
Change-Id: Ib9ac8a59e93e01365001b0d11fee41f7c507c08e
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Rename the FF-A specification to:
Arm Firmware Framework for Arm A-profile
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I4f9d29409d048e7a49832b95d39d2583c1fb5792
Joanna Farley
Manish Pandey
Madhukar Pappireddy
Olivier Deprez
Davidson K
Stas Sergeev
Penny Jan
Masahisa Kojima
Dawei Chien
Julius Werner
André Przywara
Mark Dykes
Jayanth Dodderi Chidanand
Marek Behún
Yann Gautier
Lionel Debieve
Saurabh Gorecha
Usama Arif