Update supported models list according to changes for v2.8 release in
ci/tf-a-ci-scripts repository
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Ica7e062db77237220bcd861837f392496db1653a
Cortex-A710 erratum 2291219 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r2p0, and is fixed in r2p1. The workaround is to set
CPUACTLR2_EL1[36] to 1 before the power down sequence that sets
CORE_PWRDN_EN. This allows the cpu to retry the power down and prevents
the deadlock. TF-A never clears this bit even if it wakes up from the
wfi in the sequence since it is not expected to do anything but retry to
power down after and the bit is cleared on reset.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I7d3a97dfac0c433c0be386c1f3d2f2e895a3f691
Cortex-X3 erratum 2313909 is a Cat B erratum that applies to revisions
r0p0 and r1p0, and is fixed in r1p1. The workaround is to set
CPUACTLR2_EL1[36] to 1 before the power down sequence that sets
CORE_PWRDN_EN. This allows the cpu to retry the power down and prevents
the deadlock. TF-A never clears this bit even if it wakes up from the
wfi in the sequence since it is not expected to do anything but retry to
power down after and the bit is cleared on reset.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN2055130/latest
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I5935b4bcd1e6712477c0d6eab2acc96d7964a35d
Neoverse-N2 erratum 2326639 is a Cat B erratum that applies to revision
r0p0 and is fixed in r0p1. The workaround is to set CPUACTLR2_EL1[36] to
1 before the power down sequence that sets CORE_PWRDN_EN. This allows
the cpu to retry the power down and prevents the deadlock. TF-A never
clears this bit even if it wakes up from the wfi in the sequence since
it is not expected to do anything but retry to power down after and the
bit is cleared on reset.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest/
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I9a325c5b9b498798e5efd5c79a4a6d5bed97c619
Platforms which implement pwr_domain_pwr_down_wfi differ substantially
in behaviour. However, different cpus require similar sequences to power
down. This patch tightens the behaviour of these platforms to end on a
wfi loop after performing platform power down. This is required so that
platforms behave more consistently on power down, in cases where the wfi
can fall through.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ie29bd3a5e654780bacb4e07a6d123ac6d2467c1f
Threat model for EL3 SPMC.
The mitigations are based on the guidance
provided in FF-A v1.1 EAC0 spec.
Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>
Change-Id: I7f4c9370b6eefe6d1a7d1afac27e8b3a7b476072
Add documentation how to build EL3 SPMC,
briefly describes all FF-A interfaces,
SP boot flow, SP Manifest, Power Management,
Boot Info Protocol, Runtime model and state
transition and Interrupt Handling.
Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>
Change-Id: I630df1d50a4621b344a09e462563eacc90109de4
The Cortex-X3 cpu port was developed before its public release when it
was known as Makalu ELP. Now that it's released we can use the official
product name.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Iebb90cf2f77330ed848a3d61c5f6928942189c5a
Arm has decided to deprecate the sgi575 and rdn1edge platforms.
The development of software and fast models for these platforms
has been discontinued. rdn1edge platform has been superseded by the
rdn2 platform, which is already supported in TF-A and CI work is
underway for this platform.
Change-Id: If2228fb73549b244c3a5b0e5746617b3f24fe771
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Add a section into documentation listing the support for High Assurance
Boot (HABv4), note on the DRAM mapping, and reference to the external
documentation.
Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Change-Id: Iaca97f4ac2595e35de2664a880394519f96eca07
In anticpation of the next Trusted Firmware release update the to newest
2.x Mbed TLS library [1].
Note that the Mbed TLS project published version 3.x some time ago.
However, as this is a major release with API breakages, upgrading to
this one might require some more involved changes in TF-A, which we are
not ready to do. We shall upgrade to Mbed TLS 3.x after the v2.8 release
of TF-A.
[1] https://github.com/Mbed-TLS/mbedtls/tree/v2.28.1
Change-Id: I7594ad062a693d2ecc3b1705e944dce2c3c43bb2
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
Code owners have been added for the Arm(R) Ethos(TM)-N NPU driver.
Change-Id: I0bda0d95151cdff5cd3a793c6c0e9ef6a9a5f50b
Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Conceptually the DT is a hardware description, as such it's independent
from the instruction set that a DT client uses. So having separate DTs
for aarch32 and aarch64 does not make sense and is not needed.
Probably due to historic reasons (a Linux bug fixed in 2016 with Linux
commit ba6dea4f7ced, in Linux v4.8) the CPU reg property was using a
different size between aarch64 and aarch32, even though the size of it
is solely governed by the parent's #address-cells property.
Consolidate this to be always 2, and always use two cells to describe
the CPU's MPIDR register.
This removes the last difference of the -aarch32 versions of the FVP
DT files, so just remove all of them. The respective versions without
that suffix can now be used with AArch32 DT clients as well.
Also remove the respective part in the documentation.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: I45d3a2cbba8e04595a741e1cf41900377952673e
Reinstate the workaround introduced in commit
9bbc03a6e0. The cited change to the SDEN
could not be found and there are no known problems with the workaround.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Iec9938f173e7565024aca798f224df339de90806
Documented steps to run DRTM implementation.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I30dd8c1088a54a8906389c2584d922862610dae0
The Arm(R) Ethos(TM)-N NPU driver now supports configuring the SMMU
streams that the NPU shall use and will therefore no longer delegate
access to these registers to the non-secure world. In order for the
driver to support this, the device tree parsing has been updated to
support parsing the allocators used by the NPU and what SMMU stream that
is associated with each allocator.
To keep track of what NPU device each allocator is associated with, the
resulting config from the device tree parsing will now group the NPU
cores and allocators into their respective NPU device.
The SMC API has been changed to allow the caller to specify what
allocator the NPU shall be configured to use and the API version has
been bumped to indicate this change.
Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Change-Id: I6ac43819133138614e3f55a014e93466fe3d5277
Neoverse Demeter CPU has been renamed to Neoverse V2 CPU.
Correspondingly, update the CPU library, file names and other
references to use the updated IP name.
Signed-off-by: Joel Goddard <joel.goddard@arm.com>
Change-Id: Ia4bf45bf47807c06f4c966861230faea420d088f
RAS_TRAP_LOWER_EL_ERR_ACCESS was used to prevent access to RAS error
record registers (RAS ERR* & RAS ERX*) from lower EL's in any security
state. To give more fine grain control per world basis re-purpose this
macro to RAS_TRAP_NS_ERR_REC_ACCESS, which will enable the trap only
if Error record registers are accessed from NS.
This will also help in future scenarios when RAS handling(in Firmware
first handling paradigm)can be offloaded to a secure partition.
This is first patch in series to refactor RAS framework in TF-A.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ifa7f60bc8c82c9960adf029001bc36c443016d5d
Return values contained in 'smc_result' structure
are shifted down by one register:
X1 written by RMM is returned to NS in X0 and
X5 is returned in X4.
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
Change-Id: I92907ac3ff3bac8554643ae7c198a4a758c38cb3
This flag will be used in BL32, to reconfigure UART parameters for
the early or crash console. By default, it is zero, as UART is
already configured in BL2.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I7b28ff489479ab04a2fade027933524cdd36e959
For product with 128MB DDR size, the OP-TEE is located at the end
of the DDR and the FIP can't be loaded at the default location
because it overlap the OP-TEE final location. So the default value
for DWL_BUFFER_BASE is invalid.
To avoid this conflict the serial boot load address = DWL_BUFFER_BASE
can be modified with a configuration flags.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ie27b87c10c57fea5d4c6200ce4f624e775b9a080
Recently new Xilinx Versal NET platform has been merged but documentation
cover only zynqmp. Fix the fragment to cover all Xilinx documentation.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I10f8f865ca8d46518135adb80ba0ba4470534529
Adds a dispatcher for ProvenCore based on the test secure payload
dispatcher.
Signed-off-by: Florian Lugou <florian.lugou@provenrun.com>
Change-Id: I978afc3af6a6f65791655685a7bc80070673c9f3
Add a new function to setup a SGI interrupt that will be used to trigger
a request for per-cpu power down when executing the PSCI SYSTEM_RESET
request. This will be used on CSS platform that require all the CPUs to
execute the CPU specific power down sequence to complete a warm reboot
sequence in which only the CPUs are power cycled.
Change-Id: I80da0f6c3cd0c5c442c82239ba1e1f773821a7f5
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
This toolchain provides multiple cross compilers and is publicly
available on https://developer.arm.com/
We build TF-A in CI using:
AArch32 bare-metal target (arm-none-eabi)
AArch64 ELF bare-metal target (aarch64-none-elf)
Change-Id: I94e13f6c1ebe3a4a58ca6c79c1605bd300b372d3
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Cortex-A78C erratum 2376749 is a Cat B erratum that applies
to revisions r0p1 and r0p2 of the A78C and is currently open.
The workaround is to set CPUACTLR2_EL1[0] to 1 to force
PLDW/PFRM ST to behave like PLD/PRFM LD and not cause
invalidations to other PE caches.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN2004089/latest
Signed-off-by: Akram Ahmad <Akram.Ahmad@arm.com>
Change-Id: I3b29f4b7f167bf499d5d11ffef91a94861bd1383
Cortex-A710 erratum 2216384 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r2p0, and is fixed in r2p1. The workaround is to set
CPUACTLR5_EL1[17] to 1 and applying an instruction patching sequence.
Setting this bit, along with these instructions will prevent the
deadlock, and thereby avoids the reset of the processor.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest
Change-Id: I2821591c23f854c12111288ad1fd1aef45db6add
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Cortex-A510 erratum 2347730 is a Cat B erratum that affects
revisions r0p0, r0p1, r0p2, r0p3, r1p0 and r1p1. It is
fixed in r1p2. The workaround is to set CPUACTLR_EL1[17]
to 1, which will disable specific microarchitectural clock
gating behaviour.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1873351/latesthttps://developer.arm.com/documentation/SDEN1873361/latest
Signed-off-by: Akram Ahmad <Akram.Ahmad@arm.com>
Change-Id: I115386284c2d91bd61515142f971e2e72de43e68
Currently, when SPMC at S-EL2 is used, we cannot use the RAS framework
to handle Group 0 interrupts. This is required on platforms where first
level of triaging needs to occur at EL3, before forwarding RAS handling
to a secure partition running atop an SPMC (hafnium).
The RAS framework depends on EHF and EHF registers for Group 0
interrupts to be trapped to EL3 when execution is both in secure world
and normal world. However, an FF-A compliant SPMC requires secure
interrupts to be trapped by the SPMC when execution is in S-EL0/S-EL1.
Consequently, the SPMC (hafnium) is incompatible with EHF, since it is
not re-entrant, and a Group 0 interrupt trapped to EL3 when execution is
in secure world, cannot be forwarded to an SP running atop SPMC.
This patch changes EHF to only register for Group 0 interrupts to be
trapped to EL3 when execution is in normal world and also makes it a
valid routing model to do so, when EL3_EXCEPTION_HANDLING is set (when
enabling the RAS framework).
Signed-off-by: Raghu Krishnamurthy <raghu.ncstate@gmail.com>
Change-Id: I72d4cf4d8ecc549a832d1c36055fbe95866747fe
Cortex-A78C erratum 2395411 is a Cat B erratum that affects
revisions r0p1 and r0p2, and is currently open. The workaround
is to set CPUACTLR2_EL1[40] to 1, which will disable folding
of demand requests into older prefetches with L2 miss requests
outstanding.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN2004089/latest
Signed-off-by: Akram Ahmad <Akram.Ahmad@arm.com>
Change-Id: I4f0fb278ac20a2eb4dd7e4efd1b1246dd85e48c4
Cortex-A510 erratum 2371937 is a Cat B erratum that applies
to revisions r0p0, r0p1, r0p2, r0p3, r1p0, and r1p1. It is
fixed in r1p2. The workaround is to set the ATOM field of
CPUECTLR_EL1 (bits [40:38]) to 0b010, which will force all
cacheable atomic operations to be executed near.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1873351/latesthttps://developer.arm.com/documentation/SDEN1873361/latest
Signed-off-by: Akram Ahmad <Akram.Ahmad@arm.com>
Change-Id: Ia219a609a3397e39631de65831ecff8a3cd1227e
Cortex-A710 erratum 2147715 is a Cat B erratum that applies
to revision r2p0 of the CPU, and is fixed in r2p1. The work-
around is to set CPUACTLR_EL1[22]=1. Setting this will cause
the CFP instruction to invalidate all branch predictor resources
regardless of the context.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest
Signed-off-by: Akram Ahmad <Akram.Ahmad@arm.com>
Change-Id: I94771bc1fc9b65a0c17d75200ec2b1df8a3279c6
FEAT_RNG_TRAP introduces support for EL3 trapping of reads of the
RNDR and RNDRRS registers, which is enabled by setting the
SCR_EL3.TRNDR bit. This patch adds a new build flag
ENABLE_FEAT_RNG_TRAP that enables the feature.
This feature is supported only in AArch64 state from Armv8.5 onwards.
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
Change-Id: Ia9f17aef3444d3822bf03809036a1f668c9f2d89
Neoverse-N2 erratum 2376738 is a Cat B erratum that applies
to revision r0p0 of the CPU. It is fixed in r0p1. The workaround
is to set CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM ST to
behave like PLD/PRFM LD and not cause invalidations to other
PE caches.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest
Signed-off-by: Akram Ahmad <Akram.Ahmad@arm.com>
Change-Id: I4ad4434f9b7210244e67046d9657d218857dced5
For A3K there are two different tools for booting Armada37x0 platform
over UART, one from Marvell and second from CZ.NIC. For A8K there is
just one my own mvebu64boot tool.
Add documentation how to build these tools and how to download TF-A
image over UART to boot TF-A without flashing it to non-volatile
storage.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Ifa03584010a9c40496a34e6d5b9f3b78cb2cc89b
The URL of the Juno Getting Started Guide has been changed.
Fix the broken link.
Signed-off-by: Arthur She <arthur.she@linaro.org>
Change-Id: I55697f2f1f787c32d1ea7dfcf9eda619906cdb5d
Neoverse-V1 erratum 1618635 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.
The workaround is done through the instruction patching
mechanism, which is performed by a write sequence of
IMPLEMENTATION DEFINED registers.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1401781/latest/
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
Change-Id: I53e406735cd3a2a930fdc72ebce3bbed97100168
Switch emails from Xilinx to AMD after acquisition.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I5d126dc49e53f2735bb7e103f8f883a9474206fc
Added a platform support to use tc2 specific CPU cores.
Signed-off-by: Rupinderjit Singh <rupinderjit.singh@arm.com>
Change-Id: Ib76d440e358e9bd1cf80aec5b8591f7a6e47ecbd
Cortex-X2 erratum 2371105 is a cat B erratum that applies to
revisions r0p0 - r2p0 and is fixed in r2p1. The workaround is to
set bit[40] of CPUACTLR2_EL1 to disable folding of demand requests
into older prefetches with L2 miss requests outstanding.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775100/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Ib4f0caac36e1ecf049871acdea45526b394b7bad
This patch adds documentation for the missing RMM-EL3
runtime services:
* RMM_RMI_REQ_COMPLETE
* RMM_GTSI_DELEGATE
* RMM_GTSI_UNDELEGATE
This patch also fixes a couple of minor bugs on return codes
for delegate/undelegate internal APIs.
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: Ic721005e7851e838eebaee7865ba78fadc3309e4
Cortex-A710 erratum 2371105 is a cat B erratum that applies to
revisions r0p0 - r2p0 and is fixed in r2p1. The workaround is to
set bit[40] of CPUACTLR2_EL1 to disable folding of demand requests
into older prefetches with L2 miss requests outstanding.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I342b095b66f808bd6c066c20c581df5341bb7c2c
laurenw-arm
Boyan Karatotev
Shruti Gupta
Manish V Badarkhe
Andrey Zhizhikin
Daniel Boulby
Mikael Olsson
Akram Ahmad
Andre Przywara
Tamas Ban
Lucian Paul-Trifu
Joel Goddard
Manish Pandey
AlexeiFedorov
Anders Dellien
Yann Gautier
Patrick Delaunay
Michal Simek
Florian Lugou
Pranav Madhu
Jayanth Dodderi Chidanand
Max Yu
Rex-BC Chen
Raghu Krishnamurthy
Juan Pablo Conde
Pali Rohár
Arthur She
Rupinderjit Singh
Bipin Ravi
Javier Almansa Sobrino