Add the associated bindings for device tree and drivers.
Change-Id: I6847df691d4b00f48d2d87a33fbf4ccd62ae5dcf
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
STM32MP2x is a new family of microprocessors designed by
STMicroelectronics and based on Arm Cortex-A35.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I741ed0a701a614817a4d0b65d3d6f4e6a79da6a9
In order to ease introduction of new STM32 MPUs platforms, a dedicated
ST sub-menu (and directory) is created.
The old page is kept, but with an orphan parameter to avoid build
issues with the docs, and to avoid listing it in the menu. It is
updated to just have links with the new pages.
A new page STM32 MPUs is created to group common options for all STM32
MPUs.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I799b57967d76a985835c7a3d9d6ab21beb44ba40
This file is common for ST platforms, move it to plat/st/common/.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I7cefbc7f857d4ea63320042988c86d28e8a3cc09
Rename PLAT_NB_FIXED_REGS to PLAT_NB_FIXED_REGUS.
This avoids confusion with regulators and registers.
Signed-off-by: Pascal Paillet <p.paillet@st.com>
Change-Id: Idb2de7204fe978ffcdd729e6cbe453e85fd089b5
Those storage macros are common to all STM32MPU chips, move them to
plat/st/common/include/stm32mp_io_storage.h
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Id20ec00ba65edf9ec7a3a89adfda307c954c3cb6
Those specific SDMMC definitions are only used in stm32_sdmmc2.c driver.
Move them there.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Iac7e505e9421aa7630bee8ce6fc2277b98581995
The function fdt_get_rcc_secure_state() is only used in BL32.
Put it under flag to avoid compilation errors.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: If57c65bef0b1a3f7349527720f94fde26edbb73c
A new local function is created to set STGEN counter value,
that will deal with __aarch64__ flag. And the function
stm32mp_stgen_get_counter is adapted for __aarch64__.
Change-Id: I53c21ad11ba5085611a028790e1decbe5994ae50
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Use read_sctlr_el3() for aarch64 code instead of read_sctlr().
Change-Id: I17b5d1f8cb2918de6ab1d2d56c15cabca0ed43fd
Signed-off-by: Yann Gautier <yann.gautier@st.com>
To have a more generic code, remove the Q from the *QSPI macros.
Change-Id: I2fa94b54054036c2175df3dfddcb76eec1119ad2
Signed-off-by: Yann Gautier <yann.gautier@st.com>
When ENABLE_RUNTIME_INSTRUMENTATION flag is set timestamps are captured
and output to the fvp console at various boot stages using the PMF
library (which are based on aarch timers).
Timestamps are captured at entry and exit points for Bl1, Bl2
and, Bl3 respectively.
Change-Id: I7c0c502e5dbf73d711700b2fe0085ca3eb9346d2
Signed-off-by: Thaddeus Serna <Thaddeus.Gonzalez-Serna@arm.com>
Cortex-X3 erratum 2742421 is a Cat B erratum that applies to
all revisions <= r1p1 and is fixed in r1p2. The workaround is to
set CPUACTLR5_EL1[56:55] to 2'b01.
SDEN documentation:
https://developer.arm.com/documentation/2055130/latest
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
Change-Id: Idadd323e419739fe909b9b68ea2dbe857846666b
Fixed internal links refrenced inside tfa/docs.
Followed https://www.sphinx-doc.org/en/master/usage/restructuredtext/roles.html#ref-role
for instrustion on how to link sections within other documents.
Signed-off-by: Thaddeus Serna <thaddeus.gonzalez-serna@arm.com>
Change-Id: I8e7c090d98951b1e3d393ab5b1d6bcdaa1865c6f
To make room for all image measurements using the
RME+SPM+TBB+MEASURED_BOOT test configuration, the Event Log's maximum
size has been significantly increased.
Change-Id: I0b9948dab893e14677bca0afa07167648a6c2729
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Maximum entries for MMAP and XLAT have been increased in order to
support the configuration SPM+RME, along with MEASURED_BOOT and
TRUSTED_BOARD_BOOT.
Change-Id: Ic0a0aefecb49d7ccc71357c4bd94e7bd2e5f57c4
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
To allow the SPD to access the Event Log on RME systems with
TrustZone Controller, the Event Log region needs to be configured
into the TZC. This change will enable read-write access of this
region from the secure world, which is currently denied.
Change-Id: I0c32977386f3d7c22f310b2b9404d48e8e6cac29
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
CCA CoT uses 'core-swd-cert' for signing all secure software, so when
using cert_create tool to generate its certificate, it throws an
error: "tools/cert_create/cert_create: unrecognized option
'--tos-fw-key-cert'".
The issue has not been seen so far since "SPM+RME+TBB+Measured-Boot"
combination is not tested in CI/local-setup. It is now resolved by
guarding usage of '--tos-fw-key-cert' for non-CCA CoTs.
Change-Id: I5e61d851a71c251920171cf410cbd0129e0e0aad
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Adds a dummy implementation of the plat_mboot_measure_key() function in
BL1 for QEMU platform.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Change-Id: I5923aad962a5e34d657cf49c177e68ed2ea93291
When BL31 software is sending data through a communication channel,
there's a chance that the final portion of the data could become
disrupted, if another software (BL32/RMM) starts setting up the
channel at the same time. To solve this issue, make sure to flush the
console data from BL31, before initializing BL32/RMM. This makes sure
that the communication stays reliable.
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: Icb8003e068b0b93bc4672e05f69001d9694a175c
The implementation of code changes manages the transmit FIFO (TxFIFO)
in the UART driver. The added code snippet includes a sequence of
instructions that ensures efficient handling of data transmission
and synchronization with the host software.
The code first checks the TxFIFO empty flag to determine whether
there is data available for transmission. If the TxFIFO is not empty,
the code waits until it becomes empty, ensuring that the transmit
operation is synchronized with the availability of data.
Subsequently, the code monitors the transmit operation's activity
status. It waits until the transmit operation becomes inactive,
indicating the completion of the previous transmission.
This synchronization step ensures that new data can be added to the
TxFIFO without causing any loss of transmission time.
Update console_flush() function, the function waits for the
Transmitter FIFO to empty and checks the transmitter's active state.
If the transmitter is in an active state, it means it is currently
shifting out a character.
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: I9d6c05bdfb9270924b40bf1f6ecb5fe541a2242e
The commit f123b91fdd ("fix(versal): fix BLXX memory
limits for user defined values") and commit a80da3899a
("fix(versal-net): fix BLXX memory limits for user defined
values") fixed issue regarding linker alignment section.
But removing -1 logic is not reflected in plat_fdt() memory
reservation code.
That's why remove +1 from prepare_dtb() not to generate a reserved
memory node with bigger size which ends up with reserving more
space than actually requested by a full featured bootloader or OS.
Change-Id: I0a646cee7d5a55157a6eb1b672c2edbe89e6a57f
Signed-off-by: Michal Simek <michal.simek@amd.com>
Bump the certifi package to a later version following an advisory [1]
affecting versions >= 2015.4.28, < 2023.7.22.
[1] https://github.com/advisories/GHSA-xqr8-7jwr-rhp7
Change-Id: Ida6ff7f0b1228728474de8695dca42303de2b305
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
move the gpc reg offset, bit define & macro to a separate header
file for code reuse.
This fixes suspend to mem on i.MX8M Plus too, since the register
layout is different there.
Change-Id: Ibec60c3a68ffa8c378de5334577a7b0e463ca875
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Marek Vasut <marex@denx.de> # Upgrade to latest, update commit message
Similar to the FVP and QEMU, the Arm FPGA systems come with different
CPU cores, and gain new features over time.
Add a list of ARMv9.2 features that require TF-A enablement to be usable
from non-secure world. Their existence will be detected at runtime, so
supporting all those features is not required for using the build.
This fixes the Linux kernel booting on a ARMv9.2 FPGA core.
Change-Id: Ie93c32b13ce4f9968081bf38296cd45edad0a928
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Memory reservation in dtb will be done only when TF-A runs from
ddr and dtb load address is provided.
Otherwise prepare_dtb will simply return.
Empty definition of prepare_dtb is removed.
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Change-Id: Ie8a3ec51d60a7389831cfe6a112f722777930623
In absence of definition, PLAT_OCM_BASE is always 0
and IS_TFA_IN_OCM(x) always returns true irrespective
of address passed to it. Reasoning is as mentioned in
Refer section 4.2.3 in
https://gcc.gnu.org/onlinedocs/gcc-3.0.2/cpp_4.html
Due to this,functionality for reservation of TF-A DDR memory in
dtb is never executed.
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Change-Id: Iafb6b7c6aec29bba22f8f7a8395f9caf97548157
In the absence of ROT_KEY option, there is no need to populate
HASH_PREREQUISITES as the build system uses the hash file specified by
ARM_ROTPK_HASH directly.
Change-Id: Ib08f53b182b8446bbc430f2608471c7dfdc0e58c
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Gabriel Fernandez
Yann Gautier
Yann Gautier
Pascal Paillet
thagon01-arm
Sona Mathew
Mark Dykes
Manish V Badarkhe
Manish Pandey
Jens Wiklander
Joanna Farley
Olivier Deprez
dependabot[bot]
Prasad Kummari
Sandrine Bailleux
Michal Simek
sahil
Harrison Mutai
Madhukar Pappireddy
Jacky Bai
Marek Vasut
Andre Przywara
Amit Nagal