Modify generic timer frequency by SCU setting
1. check SCU_CPU_HW_STRAP1 using HPLL or MPLL
SCU_CPU_HW_STRAP1[4]=1, using HPLL
SCU_CPU_HW_STRAP1[4]=0, using MPLL
2. read HPLL or MPLL
HPLL: frequency setting in SCU_CPU_HW_STRAP1[2:3]
MPLL: CLKIN_25M with mul and div setting from SCU_CPU_MPLL
Change-Id: I31eb10107b9da7c6746887ba36ead8ca61d86aae
Signed-off-by: Kevin Chen <kevin_chen@aspeedtech.com>
The oscillator clock objects will be used to describe the FIRC, FXOSC,
and SIRC clocks, all of which are oscillators on S32CC SoCs.
Change-Id: Icf235cc9b8f1d95d2c0051ce9a7655fd120289b8
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
The clock IDs are organized into categories, which are determined based
on the first 2 MSB bits for each ID. Currently, there are two big
categories: hardware and software-defined clocks.
The first category refers to clock IDs understood by the S32CC PLL muxes
and MC_CGM module muxes and is immutable. The last category of the
clocks includes software-defined IDs for clocks to allow an easy
representation of the hierarchy.
Change-Id: Idc079feb3ca5f92d8bf337ef09efad006e267088
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
This change avoids generating a build message source file on the shell,
instead using the `__DATE__` and `__TIME__` macros directly.
Change-Id: Ida537d4c3e550f2fbbd977472ed6573491d17c23
Signed-off-by: Chris Kay <chris.kay@arm.com>
This change avoids generating a build message source file on the shell,
instead using the `__DATE__` and `__TIME__` macros directly.
Change-Id: Ieda75bbac174847c716701bce8dd10b8e9975902
Signed-off-by: Chris Kay <chris.kay@arm.com>
After disabling assertion with -DENABLE_ASSERTIONS=0, the build reports
error:
drivers/arm/mhu/mhu_wrapper_v3_x.c: In function 'mhu_get_max_message_size':
drivers/arm/mhu/mhu_wrapper_v3_x.c:448:31: error: variable 'err' set but not used [-Werror=unused-but-set-variable]
enum mhu_v3_x_error_t err;
^~~
This commit fixes the building failure by making the variable 'err' as
__maybe_unused.
Change-Id: I338e6df03d2f0805c83e96d8e3a4abae41e68678
Signed-off-by: Leo Yan <leo.yan@arm.com>
To enable early clocks, such as A53, XBAR, and others, the clock driver
compilation should be included as part of the BL2 stage.
Change-Id: I17ba195d8c3cf3f91bd333a00d4a4af2f1f472b7
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
The S32CC is an umbrella for S32G2, S32G3 and S32R45 SoCs; therefore,
this clock driver will be used for all of these families.
Change-Id: Iede5371b212b67cf494a033c62fbfdcbe9b1a879
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
This driver manages the resets of the peripherals embedded in STM32MP2.
Like clock driver, it also uses the RCC peripheral.
Change-Id: I8217891bdf1b847925aad77f3f6ef542f08d1fba
Signed-off-by: Yann Gautier <yann.gautier@st.com>
This driver manages the clocks on STM32MP2 platforms.
It uses a dedicated RCC (Reset and Clock Control) peripheral.
Change-Id: I6ba2173e73222269a2dfca4c6897229276a150c0
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Fix some clocks and reset binding values.
Change-Id: Ibe480aa77cd0abb63d08bbee08ad4ec9d5d2a397
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Add the system reset management into the stm32mp
reset driver.
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: I748f10de2398e1323160f479f99e92abd2f65dca
Fix the code related error message when user provides RESET_TO_BL31=1 to
the make command but fails to provide "ARM_PRELOADED_DTB_BASE" macro at
the same command line. Remove the line break from the error string
causing the code error.
Additionally, make doesn't parse quote marks in strings, thus remove
quote marks within error strings in this file.
Change-Id: Ic131b6febebfb420ed588fe4fb0853cbdae0afb8
Signed-off-by: Salman Nabi <salman.nabi@arm.com>
Enabling Link Time Optimization in platform.mk for AMD-Xilinx
ZynqMP platform optimizes TF-A size.
With ENABLE_LTO=0, the release bl31.elf size is 86098.
With ENABLE_LTO=1, the release bl31.elf size reduces to 81866.
The size difference in OCM is 4232 bytes, saving up to 4KB.
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: I6d5001a9ac250e3a87b958e9b665962a917265d6
We have fdt_read_uint32_default() function which allows us to use less
temporary variables. Let make use of it where applicable.
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I6fc8a87d5aac427703fd3c8b689e153ed58fa8b7
Rename GENMASK parameters for better readability to avoid
misinterpreting the 'l' as '1' in BIT(l) usage.
Change-Id: I9a85c750607e098939d70c61c2e29f4788b99016
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Redefine GENMASK_32 and GENMASK_64 to avoid the impact of CWE-190, which
applies due to (~0 << (l)) syntax, where a wraparound occurs.
Change-Id: I8d08911664db7052351312d310566bb546dfb486
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
MISRA interprets all unsigned integer literals as UTLR, which has the
lowest rank required to represent a value. In this specific case, the
value 1U was interpreted as an unsigned char. As a result, explicit
casts are necessary to avoid issues with MISRA 12.2.
Change-Id: I4c1231ffabb27442c6a48dabd96942574d27c719
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
BIT_32 macro is already defined as part of the utils_def.h and included
through mmc.h
Suggested-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I7921681ee9af7d65e8eab5a0bf1d5236ecfed1a4
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
We add the support for adding cpus/topology to device tree in sbsaQemu
platform, and we can get this information via SMC calls:
- counting the number of sockets
- counting the number of clusters in one socket
- counting the number of cores in one cluster
- counting the number of threads in one core
Signed-off-by: Xiong Yining <xiongyining1480@phytium.com.cn>
Change-Id: I0059a5c7bb7055aba1aa5ec5bfd0ec78801874f8
Currently MDCR_EL3 register value is same for all the
worlds(Non-secure, Secure, Realm and Root).
With this approach, features enable/disable settings
remain same across all the worlds. This is not ideal as
there must be flexibility in controlling feature as per
the requirements for individual world.
The patch addresses this by providing MDCR_EL3 a per world
value. Features with identical values for all the worlds are
grouped under ``manage_extensions_common`` API.
Change-Id: Ibc068d985fe165d8cb6d0ffb84119bffd743b3d1
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
With PLM firmware version 2024.1 the bl32 load address is set
correctly in handoff parameters.
Hence the check to initialize bl32 load address when bl32
load address is indicated as 0 in handoff is removed.
Change-Id: I322b8d2fc1137297142704ea1087c185e16177cc
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
With PLM firmware version 2024.1 the bl32 load address is set
correctly in handoff parameters.
Hence the check to initialize bl32 load address when bl32
load address is indicated as 0 in handoff is removed.
Change-Id: Ie927787129816e79d43ba4803f6916e20d81458a
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
This patch replaces the suffix "stm32mp1_" in the SYSCFG drivers
with "stm32mp_". By using a common suffix for function names, we can
avoid issues or platform compilation flags when a driver
needs to access SYSCFG across different platforms.
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: I24407852c085abd843ef4cdef235c022a5e57a85
Newer cores implemented in the FPGAs used by Arm Ltd. support more
ARMv9 features.
Enable TCR2, MTE, MTE2, SME and SME2 as "enable if available" (:=2), so
any users of those features in lower ELs will not trigger a trap into
BL31.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: Id99ecb7c5d6a25b77f7cc5fcad63f60027a4fd5a
The ARMv8 ARM J.a describes the ID_AA64DFR0_EL1.PMUver field as allowing
a maximum version number of 8 now. The added features extend the Common
event number space and clarify on some UNPREDICTABLE behaviour.
None of this affects TF-A or any system registers, so just increase the
maximum known version number to let the FEATURE_DETECTION test pass on
ARMv8.8 implementations.
Change-Id: Icab48630c1635bcd78a710b443f0db01b8ff7c9b
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
GIC DT node structure depends on system architecture, notably around
"reg" property. A generic way to retrieve base address is needed. Use
fdt_node_offset_by_compatible() helper.
Change-Id: Ibb47864bd5e8a76a48b9346fdcf87d31281517ce
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
GPT library function fill_l1_tbl() gets 'first' and
'last' parameters which are the start addresses of
the 1st and the last granules in the range to fill
L1 GPT table. When RME_GPT_MAX_BLOCK build option
is not 0, condition for 'while' loop should be
changed from 'first < last' to 'first <= last' in
the case of 'first' = 'last' when a single granule
is passed.
Change-Id: I9b49a78b5a2f7a01f51dbce43bd3f3cfbb458fa2
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
In order to register DEV_IRQ as secure interrupt in OP-TEE, the the GICD
EnableGrp1S should be enabled for DEV_IRQ. Add mtk_interrupt_props in
MTK GIC driver to configure the interrupt properly.
Signed-off-by: Gavin Liu <gavin.liu@mediatek.com>
Change-Id: Id909a42b535088c6d0dcaf803d3f2faf312ae846
When the verify_signature function is called with the RSASSA_PSS
signature algorithm and a somewhat well-formed public key, invalid
signatures can be incorrectly verified due to this change [1].
This is primarily because of the introduction of the following code,
where a return check is missing before the goto:
if (pk_alg == MBEDTLS_PK_RSASSA_PSS) {
rc = pk_bytes_from_subpubkey((unsigned char **) &pk_ptr, &pk_len);
goto end2;
}
This code executes before the call to psa_verify_message. The
unconditional goto end2; branch leads to the immediate return of rc.
If the call to pk_bytes_from_subpubkey succeeds (i.e., the key is
formatted correctly), the signature is verified regardless of its
actual content.
This change [1] was included in the v2.11 release. Therefore, anyone
using this release with the PSA Crypto implementation must apply
this patch to ensure proper signature verification.
[1]: https://review.trustedfirmware.org/plugins/gitiles/TF-A/
trusted-firmware-a/+/55aed7d798f3d48d6aa08d58eb46c4cda318bcfb/drivers/
auth/mbedtls/mbedtls_psa_crypto.c#447
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Reported-by: Ryan Everett <ryan.everett@arm.com>
Change-Id: Ib484d97a04b7a82dd72592c8b5b153d577d01fc9
Manish V Badarkhe
Kevin Chen
Yann Gautier
Ghennadi Procopciuc
Chris Kay
Madhukar Pappireddy
Leo Yan
Manish Pandey
Gabriel Fernandez
André Przywara
Lionel Debieve
Salman Nabi
Govindraj Raja
Soby Mathew
Prasad Kummari
Marcin Juszkiewicz
Olivier Deprez
Xiong Yining
Jayanth Dodderi Chidanand
Joanna Farley
Amit Nagal
Maxime Méré
Nicolas Le Bayon
AlexeiFedorov
Gavin Liu