github/arm-trusted-firmware - arm-trusted-firmware - Gitea: Git with home nas server

Author	SHA1	Message	Date
Andre Przywara	d23acc9e4f	refactor(amu): unify ENABLE_AMU and ENABLE_FEAT_AMUv1 So far we have the ENABLE_AMU build option to include AMU register handling code for enabling and context switch. There is also an ENABLE_FEAT_AMUv1 option, solely to protect the HAFGRTR_EL2 system register handling. The latter needs some alignment with the new feature scheme, but it conceptually overlaps with the ENABLE_AMU option. Since there is no real need for two separate options, unify both into a new ENABLE_FEAT_AMU name in a first step. This is mostly just renaming at this point, a subsequent patch will make use of the new feature handling scheme. Change-Id: I97d8a55bdee2ed1e1509fa9f2b09fd0bdd82736e Signed-off-by: Andre Przywara <andre.przywara@arm.com>	2 years ago
Chris Kay	68120783d6	feat(mpmm): add support for MPMM MPMM - the Maximum Power Mitigation Mechanism - is an optional microarchitectural feature present on some Armv9-A cores, introduced with the Cortex-X2, Cortex-A710 and Cortex-A510 cores. MPMM allows the SoC firmware to detect and limit high activity events to assist in SoC processor power domain dynamic power budgeting and limit the triggering of whole-rail (i.e. clock chopping) responses to overcurrent conditions. This feature is enabled via the `ENABLE_MPMM` build option. Configuration can be done via FCONF by enabling `ENABLE_MPMM_FCONF`, or by via the plaform-implemented `plat_mpmm_topology` function. Change-Id: I77da82808ad4744ece8263f0bf215c5a091c3167 Signed-off-by: Chris Kay <chris.kay@arm.com>	4 years ago
Chris Kay	742ca2307f	feat(amu): enable per-core AMU auxiliary counters This change makes AMU auxiliary counters configurable on a per-core basis, controlled by `ENABLE_AMU_AUXILIARY_COUNTERS`. Auxiliary counters can be described via the `HW_CONFIG` device tree if the `ENABLE_AMU_FCONF` build option is enabled, or the platform must otherwise implement the `plat_amu_topology` function. A new phandle property for `cpu` nodes (`amu`) has been introduced to the `HW_CONFIG` specification to allow CPUs to describe the view of their own AMU: ``` cpu0: cpu@0 { ... amu = <&cpu0_amu>; }; ``` Multiple cores may share an `amu` handle if they implement the same set of auxiliary counters. AMU counters are described for one or more AMUs through the use of a new `amus` node: ``` amus { cpu0_amu: amu-0 { #address-cells = <1>; #size-cells = <0>; counter@0 { reg = <0>; enable-at-el3; }; counter@n { reg = <n>; ... }; }; }; ``` This structure describes the auxiliary (group 1) AMU counters. Architected counters have architecturally-defined behaviour, and as such do not require DTB entries. These `counter` nodes support two properties: - The `reg` property represents the counter register index. - The presence of the `enable-at-el3` property determines whether the firmware should enable the counter prior to exiting EL3. Change-Id: Ie43aee010518c5725a3b338a4899b0857caf4c28 Signed-off-by: Chris Kay <chris.kay@arm.com>	3 years ago
Chris Kay	9cf7564723	docs(amu): add AMU documentation This change adds some documentation on the AMU and its purpose. This is expanded on in later patches. Change-Id: If2834676790938d8da5ea2ceba37b674f6cc0f01 Signed-off-by: Chris Kay <chris.kay@arm.com>	3 years ago