github/arm-trusted-firmware - arm-trusted-firmware - Gitea: Git with home nas server

Author	SHA1	Message	Date
Hadi Asyrafi	3f7b1490dc	intel: Platform common code refactor Pull out common code from aarch64 and include Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I4d0f5e1bb01bcdacbedf8e6c359de594239b645f	5 years ago
Hadi Asyrafi	d8820789ca	intel: Platform common code refactor Pull out common code from agilex and stratix10 Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Iddc0a9e6eccb30823d7b15615d5ce9c6bedb2abc	5 years ago
Ambroise Vincent	5b6ebeec9c	Remove MULTI_CONSOLE_API flag and references to it The new API becomes the default one. Change-Id: Ic1d602da3dff4f4ebbcc158b885295c902a24fec Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>	6 years ago
Hadi Asyrafi	bf719f66a7	intel: Pull out common drivers into platform common Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ib79e2c6fe6e66dec5004701133ad6a5f4c78f2fa	5 years ago
Muhammad Hadi Asyrafi Abdul Halim	10e70f87e0	intel: Enable watchdog timer on Intel S10 platform Watchdog driver support & enablement during platform setup Signed-off-by: Muhammad Hadi Asyrafi Abdul Halim <muhammad.hadi.asyrafi.abdul.halim@intel.com>	6 years ago
Muhammad Hadi Asyrafi Abdul Halim	f5ba408c34	intel: QSPI boot enablement Manages QSPI initialization, configuration and IO handling as boot device Signed-off-by: Muhammad Hadi Asyrafi Abdul Halim <muhammad.hadi.asyrafi.abdul.halim@intel.com>	6 years ago
Tien Hock, Loh	1cf55aba49	plat: intel: Add BL31 support to Intel Stratix10 SoCFPGA platform This adds BL31 support to Intel Stratix10 SoCFPGA platform. BL31 in TF-A supports: - PSCI calls to enable 4 CPU cores - PSCI mailbox calls for FPGA reconfiguration Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>	6 years ago
Loh Tien Hock	9d82ef26c6	plat: intel: Add BL2 support for Stratix 10 SoC This adds BL2 support for Intel Stratix 10 SoC FPGA. Functionality includes: - Release and setup peripherals from reset - Calibrate DDR - ECC DDR Scrubbing - Load FIP (bl31 and bl33) Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>	6 years ago