The code was already removed as part of commit 4ac5b3949d
"refactor(auth): replace plat_convert_pk". The present commit just
removes it from the release documentation.
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: I06b35f110c844267d69a865df55dd451ed2f08cd
In assembly code, BIT macro is used with a preceding hash #. Let's
update Cortex X1 code to follow the same convention. Excluding hash
doesn't cause compilation to fail or emit incorrect code.
Signed-off-by: Okash Khawaja <okash@google.com>
Change-Id: If304cdf90542d2edcab3e2d66cd7e905ff7fd047
FVP currently does not have proper handler to do Firmware First Handling
(FFH) of lower EL External aborts and it ends up in EL3 panic.
To test the scenarios sensibly we need a proper handling when the FVP is
under test so that we do not change the default behavior.
Introduce PLATFORM_TEST_EA_FFH config which will be enabled in CI
scripts and implement a proper handling for Sync EA and SErrors from
lower EL.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ib130154206b17f72c49c9f07de2d92f35a97ab0b
QEMU 7.2+ has FEAT_FGT support added to 'max' cpu.
So let's enable it to make Debian 'bookworm' kernel boot on sbsa-ref/max setup.
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I49fb3e742b69ce7be5666e0144525dde21a68238
FEAT_SME2 is an extension of FEAT_SME and an optional feature
from v9.2. Its an extension of SME, wherein it not only
processes matrix operations efficiently, but also provides
outer-product instructions to accelerate matrix operations.
It affords instructions for multi-vector operations.
Further, it adds an 512 bit architectural register ZT0.
This patch implements all the changes introduced with FEAT_SME2
to ensure that the instructions are allowed to access ZT0
register from Non-secure lower exception levels.
Additionally, it adds support to ensure FEAT_SME2 is aligned
with the existing FEATURE DETECTION mechanism, and documented.
Change-Id: Iee0f61943304a9cfc3db8f986047b1321d0a6463
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Macro esb used in TF-A executes the instruction "esb" and is kept under
RAS_EXTENSION macro. RAS_EXTENSION, as it stands today, is only enabled
for platforms which wants RAS errors to be handled in Firmware while esb
instruction is available when RAS architecture feature is present
irrespective of its handling.
Currently TF-A does not have mechanism to detect whether RAS is present
or not in HW, define this macro unconditionally.
Its harmless for non-RAS cores as this instruction executes as NOP.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I556f2bcf5669c378bda05909525a0a4f96c7b336
As per recent changes to OPTEE's fvp.mk file, both options
"MEASURED_BOOT" and "MEASURED_BOOT_FTPM" are required for the fTPM
application to be built.
Change-Id: I621113c3fbd47e9f5be015ea65e9b8d0f218e4e8
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
The C preprocessor cannot compare defines against strings.
Such an expression is always evaluated to be true. Therefore,
its usage in a conditional expression results that always the
first branch is taken. Other branches cannot be reached by
any configuration value. The fix removes this string comparison
and instead it introduces distinct defines for all the cases.
Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: Ia1142b31b6778686c74e1e882fe4604fe3b6501d
Recently mbedtls_cofig.h was renamed to:
- mbedtls_config-2.h
- mbedtls_config-3.h
Modify the include order to resolve the
static check failure in the CI.
Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I424f1cde199397b8df780a9514f1042e601c6502
This patch implements the pwr_domain_off_early handler for
Tegra platforms.
Powering off the boot core on some Tegra platforms is not
allowed and the SOC specific helper functions for Tegra194,
Tegra210 and Tegra186 implement this restriction.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I9d06e0eee12314764adb0422e023a5bec6ed9c1e
* changes:
feat(ti): synchronize access to secure proxy threads
refactor(ti): remove inline directive from ti_sci and sec_proxy drivers
refactor(ti): refactor ti_sci_{setup,do}_xfer to allow zero size response
feat(ti): add sub and patch version number support
The Allwinner T507 SoC is using the same die as the H616, but in a
different package. On top of this, there is at least one different die
revision out there, which uses a different CPU cluster control block.
The same die revision has been spotted in some, but not all, H313 SoCs.
Apart from that IP block, the rest of the SoC seems the same, so we can
support them using the existing H616 port. The die revision can be
auto-detected, so there is no extra build option or knowledge needed.
Provide the deviating CPU power up/down sequence for the die variant.
The new IP block uses per-core instead of per-cluster registers, but
follows the same pattern otherwise.
Since the CPU ops code is shared among all Allwinner SoCs, we need to
dummy-define the new register names for the older SoCs. The actual new
code is guarded by a predicate function, that is hard coded to return
true on the other SoCs. Since this is a static inline function in a
header file, the compiler will optimise away the unneeded branch there,
so the generated code for the other SoCs stays the same.
Change-Id: Ib5ade99d34b4ccb161ccde0e34f280ca6bd16ecd
Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Allwinner provides a number of SoCs that use the same die as the H616.
Some of those chips apparently use a slight variation of that die, that
differs in the way the CPU cores' power and reset controls are handled.
This die variation can be detected by reading the SRAM version register.
Provide a predicate function that returns false if that die variant is
used. Since the CPU power control code is shared for all supported SoCs,
we provide an instance of this function for each SoC, as a static
inline, and return true on all other SoCs. This allows to always use
this function, and still let the compiler optimise away the unneeded
branch for those older SoCs.
This function is unused for now, but is needed in the next patch.
Change-Id: I49e014b895b7e2f55b4e7dc2b3d8aa31cee711b5
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The die used in several variants of the Allwinner H616 SoC (H313, T507)
seems to produced in at least two revisions. The newer one differs from
the original by using a different CPU control register IP block.
Add those newly used register offsets to the respective header file. The
MMIO block itself is actually present in both variants, though the
registers are different. The new registers tend to use one register per
core, in contrast to one register per cluster in the older revisions.
Change-Id: Ifbda1bdc67a6a16fbb901dbc83996e4a148b7602
Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The header files describing the CPU cluster configuration IP block for
the H6 and H616 are actually identical, so merge them into one file and
move that to a common location. There is an upcoming SoC which will
similarly share a header file with the R329 SoC, so move that to the
same location already. In Allwinner's BSP source those two SoC groups
are typically called "NCAT" and "NCAT2", so use those names for the
shared header files. No functional change.
Change-Id: I98318373577344dbe228a81fa331ce660df32b5f
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The fvp build includes a very large number of cpus so that it can run on
a wide range of models. One config (HW_ASSISTED_COHERENCY=1
CTX_INCLUDE_AARCH32_REGS=0) includes an unusually large number of cpus.
Well, the list is quite arbitrary and incomplete. As we're currently out
of BL31 space on the fvp, remove all that are not routinely run in the
CI to buy us some time.
Also use the opportunity to reorder the list into something searchable.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I8c6cad41327451edf0d3a0e92c43d6c72c254aac
* changes:
build(trp): sort sections by alignment by default
build(tsp): sort sections by alignment by default
build(sp-min): sort sections by alignment by default
build(bl31): sort sections by alignment by default
build(bl2u): sort sections by alignment by default
build(bl2): sort sections by alignment by default
This patch introduces the 'pwr_domain_off_early' hook for
platforms wanting to perform housekeeping steps before the
PSCI framework starts the CPU power off sequence. Platforms
might also want to use ths opportunity to ensure that the
CPU off sequence can proceed.
The PSCI framework expects a return code of PSCI_E_DENIED,
if the platform wants to halt the CPU off sequence.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I6980e84fc4d6cb80537a178d0d3d26fb28a13853
Use the same format in all files 's/Copyright (C)/Copyright (c)/g'.
Change-Id: I0e200eb135e7369d0e6b3b694acd406ec10ca9e7
Signed-off-by: Michal Simek <michal.simek@amd.com>
Host must only set UICCMD if HCS.UCRDY is set to 1.
At present, SW polls for UCRDY only before sending DME_GET.
Generalise this behaviour for DME_SET, DME_LINKSTARTUP,
DME_HIBERNATE_EXIT by moving polling logic inside ufshc_send_uic_cmd.
Signed-off-by: Rohit Ner <rohitner@google.com>
Change-Id: Iece777f803a660fdd144a073834c221e889371a6
Some parts of the documentation referring to Poetry provides incorrect
build instructions and has some minor formatting errors. Reformat the
bits that require formatting, and fix the build instructions. These
were originally part of the patch stack that added Poetry support but
were accidentally reverted prior to merge.
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Change-Id: I336d3a7bbe99f75262430ae436f8ebc2cb050d2c
At the moment we only support FEAT_DIT to be either unconditionally
compiled in, or to be not supported at all.
Add support for runtime detection (ENABLE_DIT=2), by splitting
is_armv8_4_dit_present() into an ID register reading function and a
second function to report the support status. That function considers
both build time settings and runtime information (if needed).
We use ENABLE_DIT in two occassions in assembly code, where we just set
the DIT bit in the DIT system register.
Protect those two cases by reading the CPU ID register when ENABLE_DIT
is set to 2.
Change the FVP platform default to the now supported dynamic
option (=2), so the right decision can be made by the code at runtime.
Change-Id: I506d352f18e23c60db8cdf08edb449f60adbe098
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Click is used in parts of the CI scripts (see run_config/fvp-linux.tc
for instance), add it back as part of a new dependency group. Future
dependencies that are required only in CI should be added to the
``ci`` dependency group.
Change-Id: I5da7fea703495dd4006d86334626f126a850bb10
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
If RAS Extension is not implemented esb instruction executes as a NOP.
No need to have a check for RAS presence in the code.
Also, The handler is related to a synchronous exceptions which
implicitly is part of BL31 image only, so remove that check too.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: If4264504cba9f0642b7b9c581ae66cd4deace32b
PLAT_SP_PRI is used by SPM_MM and it is assigned same value as RAS
priority. Which is not allowed by exception handling framework and
causes build failure if both SPM_MM and RAS is enabled.
To fix this problem assign SP a different priority than RAS.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Iff64ac547f0966c0d94ac7c3ab0eb1e3151fb314
* changes:
refactor(auth)!: unify REGISTER_CRYPTO_LIB
refactor(auth): replace plat_convert_pk
docs(auth): add auth_decrypt in CM chapter
feat(auth): compare platform and certificate ROTPK for authentication
docs(auth): add 'calc_hash' function's details in CM
Sandrine Bailleux
Manish Pandey
Okash Khawaja
Manish V Badarkhe
Marcin Juszkiewicz
Joanna Farley
Jayanth Dodderi Chidanand
Tamas Ban
Madhukar Pappireddy
Varun Wadekar
Mikhail Kalashnikov
Andre Przywara
Boyan Karatotev
Chris Kay
Michal Simek
Rohit Ner
Harrison Mutai
Bipin Ravi