Adds a check to pre-commit hook that makes sure "Arm" is written in a
correct case and not "arm" or "ARM". Same as a copyright-year check, the
hook will fix the issue and prompt user to stage the fix.
Change-Id: I39db148d6621d542193f3ee703bddc23c7e8dc27
Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
BL2_AT_EL3 is an overloaded macro which has two uses:
1. When BL2 is entry point into TF-A(no BL1)
2. When BL2 is running at EL3 exception level
These two scenarios are not exactly same even though first implicitly
means second to be true. To distinguish between these two use cases we
introduce new macros.
BL2_AT_EL3 is renamed to RESET_TO_BL2 to better convey both 1. and 2.
Additional macro BL2_RUNS_AT_EL3 is added to cover all scenarious where
BL2 runs at EL3 (including four world systems).
BREAKING CHANGE: BL2_AT_EL3 renamed to RESET_TO_BL2 across the
repository.
Change-Id: I477e1d0f843b44b799c216670e028fcb3509fb72
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
Adds a common function to poll for interrupt status which reports errors
and returns error codes
Signed-off-by: Anand Saminathan <anans@google.com>
Change-Id: Ie5df036dc979e984871de4ae7e974b994296ca4c
Added silicon revision in the platform information SDS structure.
Implemented platform functions to retrieve the soc-id information
for the morello SoC platform. SoC revision, which is same as
silicon revision, is fetched from the morello_plat_info structure
and SoC version is populated with the part number from SSC_VERSION
register, and is reflected in bits[0:15] of soc-id.
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Change-Id: I8e0c5b2bc21e393e6d638858cc2ea9f4638f04b9
Currently isr is not called when IPI0 interrupt occurs.
fix irq number and enable GIC interrupt properly to invoke
registered isr on IPI0 interrupt.
Signed-off-by: Trung Tran <trung.tran@amd.com>
Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Change-Id: Id0408b3a560b25234886a9fa01c4ed248d1d1532
Users of GNU ld (BPF) from binutils 2.39+ will observe multiple instaces
of a new warning when linking the bl*.elf in the form:
ld.bfd: warning: stm32mp1_helper.o: missing .note.GNU-stack section implies executable stack
ld.bfd: NOTE: This behaviour is deprecated and will be removed in a future version of the linker
ld.bfd: warning: bl2.elf has a LOAD segment with RWX permissions
ld.bfd: warning: bl32.elf has a LOAD segment with RWX permissions
These new warnings are enbaled by default to secure elf binaries:
- https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=ba951afb99912da01a6e8434126b8fac7aa75107
- https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=0d38576a34ec64a1b4500c9277a8e9d0f07e6774
Fix it in a similar way to what the Linux kernel does, see:
https://lore.kernel.org/all/20220810222442.2296651-1-ndesaulniers@google.com/
Following the reasoning there, we set "-z noexecstack" for all linkers
(although LLVM's LLD defaults to it) and optional add
--no-warn-rwx-segments since this a ld.bfd related.
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Robert Schwebel <r.schwebel@pengutronix.de>
Change-Id: I9430f5fa5036ca88da46cd3b945754d62616b617
This is a small helper to check for possible linker options. If the
linker supports the requested option it is returned and if not nothing
will be returned, e.g.:
TF_LDFLAGS += $(call ld_option, --no-warn-rwx-segments)
can be called unconditional.
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-Id: I236800852ece49948ff53a0b91fddba53c8f0f95
Add support to qemu "neoverse-n1" cpu for "qemu_sbsa" ('sbsa-ref')
platform.
Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
Change-Id: I4620e879c71115451ae91a1643812d89ec7c071f
Since CPUs such as cortex-a76 are hardware-assisted coherent, coherent
memory section is not required for them and should be an optional
section.
Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
Change-Id: I03c8e9148ca1780b8af92024359698f4452f7129
Use the setup_page_tables() helper function to setup page tables.
Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
Change-Id: I0bca4e463ed68abf2ef1c79fc8e5cb2b635fcd1c
Neoverse V1 erratum 2743233 is a Cat B erratum that applies to
all revisions <= r1p2 and is still open.
The workaround sets CPUACTLR5_EL1[56:55] to 2'b01.
SDEN documentation: https://developer.arm.com/documentation/SDEN1401781/latest
Change-Id: If51a6f4293fa8b5b35c44edd564ebb715ba309a1
Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>
This patch introduces a workaround to support the legacy SMC FID
0xC2FEFE00 to maintain compatibility with older software components.
Change-Id: Icf2ef9cfa6b28c09bbab325a642d0b3b20b23535
Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com>
This patch appends the chip's major revision to the chip id value
to form the SoC version value expected by the SMCCC_GET_SOC_VERSION
function ID.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I09118f446f6b8198588826d4a161bd97dcb6a581
This adds return of a UUID when TF-A is in the state where it needs to
receive the SMC call to load the OP-TEE image. It also changes the OEN
used for the image loading call to match the OEN used for the UUID call.
Signed-off-by: Jeffrey Kardatzke <jkardatzke@google.com>
Change-Id: I713cb602d8e53b3f20d179b5fb5162da6a2ed057
* changes:
feat(imx8mq): enable dram dvfs support on imx8mq
feat(imx8m): use non-fast wakeup stop mode for system suspend
feat(imx8mq): correct the slot ack setting for STOP mode
feat(imx8mq): add anamix pll override setting for DSM mode
feat(imx8mq): add workaround code for ERR11171 on imx8mq
feat(imx8mq): add the dram retention support for imx8mq
feat(imx8mq): add version for B2
fix(imx8m): backup mr12/14 value from lpddr4 chip
fix(imx8m): add ddr4 dvfs sw workaround for ERR050712
fix(imx8m): fix coverity out of bound access issue
fix(imx8m): fix the dram retention random hang on some imx8mq Rev2.0
feat(imx8m): add more dram pll setting
fix(imx8m): fix the current fsp init
fix(imx8m): fix the rank to rank space issue
fix(imx8m): fix the dfiphymaster setting after dvfs
feat(imx8m): update the ddr4 dvfs flow to include ddr3l support
fix(imx8m): correct the rank info get fro mstr
feat(imx8m): fix the ddr4 dvfs random hang on imx8m
The documentation has been updated to explicitly mention that with
RESET_TO_BL31, the platform can receive parameters based on their
actual boot sequence.
Change-Id: Ib482fb89e528ec836ff7ee175cac59dd2da2898b
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
It was assumed that BL31 is the first bootloader to run so there's
no argument to relay from a previous bootloader in RESET_TO_BL31
case, however this is not true for every platform with a non-TF-A
bootloader that might get executed before BL31 while compiling in
RESET_TO_BL31 feature.
Thus, by avoiding zeroing registers, the arguments passed from the
previous bootloader to BL31 are preserved.
Change-Id: I7bb66a10d1fd551ba3fd59a7a38ab5bde3197f72
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Adopted RESET_TO_BL31_WITH_PARAMS functionality in RESET_TO_BL31
in the subsequent patches hence reverted this patch.
This reverts commit ac4ac38c54.
Change-Id: I5fb8eaea47d0fd6d0171260c6d834ec8de588fad
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Adopted RESET_TO_BL31_WITH_PARAMS functionality in RESET_TO_BL31
in the subsequent patches hence reverted this patch.
This reverts commit 25844ff728.
Change-Id: Ia0bfa22fc45754f15c82638662dde93f604992c3
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Currently, if CRC validation fails during IPI communication,
pm_ipi_buff_read_callb() logs error message but don't return
error code to upper layers.
Added CRC failure specific error code which will be returned by
pm_ipi_buff_read_callb() if CRC validation fails.
Signed-off-by: Naman Trivedi Manojbhai <naman.trivedimanojbhai@amd.com>
Change-Id: I2eaca073e2bf325a8c86b1820bdd7cca487b783e
Currently, if CRC validation fails during IPI communication,
pm_ipi_buff_read() logs error message but don't return error
code to upper layers.
Added CRC failure specific error code which will be returned by
pm_ipi_buff_read() if CRC validation fails.
Signed-off-by: Naman Trivedi Manojbhai <naman.trivedimanojbhai@amd.com>
Change-Id: I33be330f276973471f4ce4115d1e1609ed8fb754
The spmd_setup function is made fail safe in that a failure in the
SPMC manifest parsing, SPMD or SPMC initialization returns a success
code to the standard services initialization routine (std_svc_setup).
This permits continuing the boot process and initialize services
beyond the SPMD to succeed for the system to operate in the normal
world. It operates in a degraded mode for the secure world.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Ida0ac91c17925279a79f112d190f9ad038f518e7
Cortex-A78C erratum 2779484 is a Cat B erratum that applies to
revisions r0p1 and r0p2 and is still open.
The workaround is to set the CPUACTLR3_EL1[47] bit to 1. Setting this
bit might have a small impact on power and negligible impact on
performance.
SDEN documentation:
https://developer.arm.com/documentation/SDEN2004089/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I9a8c16a845c3ba6eb2f17a5119aa6ca09a0d27ed
Cortex-A78 erratum 2742426 is a Cat B erratum that applies to
all revisions <= r1p2 and is still open.
The workaround is to set the CPUACTLR5_EL1[56:55] to 2'b01.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1401784/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I42506a87d41c9e2b30bc78c08d22f36e1f9635c1
Copied the Event Log from internal SRAM to the TZC secured DRAM
reserved area. Also passed this Trusted DRAM address to OPTEE via
NT FW configuration, and to SPMC via TOS FW configuration,
which is eventually used to extend PCR via fTPM application running
on top of OPTEE/SPMC.
Furthermore, this patch makes it easier to access Event Log in RME
enabled systems where Secure World firmware does not have access to
internal(Root) SRAM.
Change-Id: I005e9da1e6075511f412bdf4d8b541fa543df9ab
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Reserved 4KB area for Event Log in DRAM1. This area is used by BL2
to copy Event Log from internal SRAM to this carved out DRAM region
in the subsequent patch.
Change-Id: I7b405775c66d249e31edf7688d95770e6c05c175
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change in PLATFORM_TEST build flag from boolean -> string, with the
current string options being tfm-testsuite and rss-nv-counters.
To get the old behavior, i.e. where we used to use PLATFORM_TEST=1,
we now need to pass PLATFORM_TEST=tfm-testsuite.
Adding new test of the AP/RSS interface for non-volatile counters.
The test reads, increments, and reads again each 3 types of NV
counters for: CCA, secure, and non-secure firmware. Enabled by
PLATFORM_TEST=rss-nv-counters.
Change-Id: I2044cc9b2f37984697e0754c9c824eab51a11e7f
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Signed-off-by: Raef Coles <raef.coles@arm.com>
Currently there is no guidelines in docs for including thirdparty
includes, trying to address that with a proposed method to use third
party includes.
Change-Id: Ieec7a5c88a60b66ca72228741ba1894545130a06
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
* This change overrides the default PLAT_ARM_FIP_OFFSET_IN_GPT
* This aligns the FIP base in GPT image to the RSS ATU page size
boundary (8 KiB). RSS XIP feature requires the FIP to be aligned to
the page size boundary. TC platform will require the XIP feature.
* The aligned FIP_A is starting at sector 48. Hence the offset will be
48*512 = 0x6000.
Signed-off-by: Tintu Thomas <tintu.thomas@arm.com>
Change-Id: I8135ecd4168231847c80151c33ef8353a1586b9a
Maksims Svecovs
Manish V Badarkhe
Joanna Farley
Manish Pandey
Arvind Ram Prakash
Anand Saminathan
Chandni Cherukuri
Trung Tran
Bipin Ravi
Varun Wadekar
Madhukar Pappireddy
Elyes Haouas
Marco Felsch
Chen Baozi
Sona Mathew
Kalyani Chidambaram Vaidyanathan
Jeffrey Kardatzke
Olivier Deprez
Naman Trivedi Manojbhai
laurenw-arm
Govindraj Raja
Tintu Thomas